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Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals

David Szczesny, Sebastian Hessel, Shadi Traboulsi, Attila Bilgic
2010 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications  
In addition to the downlink processing, we analyse different on-the-fly hardware acceleration modes for the uplink protocol stack processing in layer 2 (L2).  ...  In this paper we present an extended and optimized version of a smart Direct Memory Access (sDMA) controller supporting different on-the-fly protocol stack acceleration concepts for Long Term Evolution  ...  Fig. 5 . 5 Hardware acceleration concepts for the LTE L2 uplink: a) conventional with a stand-alone hardware accelerator b) on-the-fly with sDMA controller by using the protocol stack descriptor format  ... 
doi:10.1109/rtcsa.2010.18 dblp:conf/rtcsa/SzczesnyHTB10 fatcat:snnfwu6wwrdn3oihfpltxmae5m

Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals

Sebastian Hessel, David Szczesny, Felix Bruns, Attila Bilgic, Josef Hausner
2010 2010 IEEE 72nd Vehicular Technology Conference - Fall  
In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP's Long Term Evolution (LTE).  ...  With a low-level hardware implementation we prove that also from an architectural point of view the sDMA controller is suitable for LTE terminals.  ...  Alternatively, a conventional hardware accelerator concept, composed of a DMA controller and a stand-alone hardware acceleration unit, can be attached to the testbench for architectural comparisons with  ... 
doi:10.1109/vetecf.2010.5594536 dblp:conf/vtc/HesselSBBH10 fatcat:du6vf55jxzgrrhtzoed4mnd2dm

Design of a high-performance RSVP-TE hardware signaling accelerator

Haobo Wang, M. Veeraraghavan, R. Karri, Tao Li
2005 IEEE Journal on Selected Areas in Communications  
To improve performance for high-speed networks, we implemented a subset of the RSVP-TE signaling protocol in reconfigurable FPGA hardware.  ...  Up to now, signaling protocols are mostly implemented in software for two reasons: complexity and the requirement for flexibility. Adversely, the price paid is in performance.  ...  ., for providing us with free samples of TCAM, SRAM, and FIFO devices, and the related simulation models.  ... 
doi:10.1109/jsac.2005.852241 fatcat:rvpldfyvvvgmhp6wgayfv7yqzm

The case for crypto protocol awareness inside the OS kernel

Matthew Burnside, Angelos D. Keromytis
2005 SIGARCH Computer Architecture News  
Separation of control and data plane is a principle increasingly used to improve the performance of network protocols and applications, such as the Web.  ...  Our intuition is that protocol framing and cryptographic transforms can be applied to incoming and outgoing data frames by the operating system under a policy specified by the web server.  ...  [4] has focused on the impact of hardware accelerators in the context of TLS web servers using a trace-based methodology, and concludes that there is some opportunity for acceleration, but given the  ... 
doi:10.1145/1055626.1055635 fatcat:fogjhb2y7vhp3aqnwfqrc3i3oq

Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors

Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
This article advocates a hardware-supported communication mechanism using a protocol-adaptive approach to adjust to varying NoC configurations (e.g., number of buffers) and workload behavior (e.g., number  ...  a synchronous protocol when buffers in the receiver are limited.  ...  Thus, a unique hardware structure is extended to accelerate list traversal and matching [Underwood et al. 2005 ].  ... 
doi:10.1145/2512434 fatcat:ydk3oakwenbtpfvvltbbv7ci4i

Countermeasure for Round Trip Delay Which Occurs in Between Satellite and Ground with Software Network Accelerator

Kohei Arai
2012 International Journal of Advanced Computer Science and Applications  
Countermeasure for round trip delay which occurs in between satellite and ground with network accelerator is investigated together with operating system dependency on effectiveness of accelerator.  ...  Also disaster relief data transmission experiments are conducted for mitigation of disaster together with acceleration of disaster related data transmission between local government and disaster prevention  ...  Ltd. for their great effort to conduct of the experiments as well as their valuable discussions we have had, as well as comments and suggestions.  ... 
doi:10.14569/ijacsa.2012.030518 fatcat:4lkbxyj5tnhufmjbgcnkksdsxm

A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Neal Oliver, Rahul R. Sharma, Stephen Chang, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra (+3 others)
2011 2011 International Conference on Reconfigurable Computing and FPGAs  
This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of non-streaming-data applications unduly difficult.  ...  ACKNOWLEDGMENTS We would like to acknowledge the contributions of partner companies Altera, Impulse Accelerated Technologies, Nallatech, Pactron, and Xilinx, in the development of these technologies.  ...  After the device finishes writing to the kernel buffer, the device driver copies data from the kernel buffer to the user buffer and provides a pointer to the user buffer to the application.  ... 
doi:10.1109/reconfig.2011.4 dblp:conf/reconfig/OliverSCCGGGILMMSSWG11 fatcat:mvjrcbxfh5dulequewmo52waoa

A hardware-accelerated implementation of the RSVP-TE signaling protocol

Haobo Wang, R. Karri, M. Veeraraghavan, Tao Li
2004 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)  
To improve performance for high-speed networks, we implemented RSVP-TE signaling protocol in reconfigurable FPGA hardware.  ...  Signaling protocols are primarily implemented in software for two reasons: protocol complexity and the requirement for flexibility.  ...  ACKNOWLEDGMENT We thank Integrated Device Technology, Inc. for providing us with free samples of TCAM, SRAM, and FIFO devices, and the related simulation models.  ... 
doi:10.1109/icc.2004.1312782 dblp:conf/icc/WangKVL04 fatcat:mh3q7at25ngx3m72qmvhrkm7ke

A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform

U. Langenbach, A. Berthe, B. Traskov, S. Weide, K. Hofmann, P. Gregorius
2013 2013 IEEE Third International Conference on Consumer Electronics ¿ Berlin (ICCE-Berlin)  
This paper presents a fully hardwired 10 GbE TCP/IP stack, designed a tightly coupled system integrating higher-level protocols and application-specific logic in order to build a fully integrated and accelerated  ...  With the increasing number of Internet services, the flexible and reliable TCP/IP protocol suite has become a standard for network communication.  ...  As a result the latency shown for the presented protocol acceleration platform reflects the minimum latency for a protocol processing accelerator derived from this platform.  ... 
doi:10.1109/icce-berlin.2013.6697997 dblp:conf/icce-berlin/LangenbachBTWHG13 fatcat:aymyiwmombgxzoayy462qor66u

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

Noboru TANABE, Atsushi OHTA
2013 IEICE transactions on information and systems  
In this paper, a support function named LHS (Limited-length Head Separation) is proposed. Its performance in searching message buffer and hardware cost are evaluated.  ...  On large-scale parallel systems, the number of accumulated messages on a message buffer tends to increase in some of their applications.  ...  ALPU [5] which is a hardware accelerator for searching message buffer has better searching performance than QsNET-II.  ... 
doi:10.1587/transinf.e96.d.2536 fatcat:bdjfobhnnfgrlntswplxtezr2u

Cryptography as an operating system service

Angelos D. Keromytis, Jason L. Wright, Theo De Raadt, Matthew Burnside
2006 ACM Transactions on Computer Systems  
Cryptographic transformations are a fundamental building block in many security applications and protocols. To improve performance, several vendors market hardware accelerator cards.  ...  We believe that this validates our decision to opt for ease of use by applications and kernel components through a uniform API and for seamless support for new accelerators.  ...  We would also like to thank Patrick McDaniel for providing high-quality shepherding of this article.  ... 
doi:10.1145/1124153.1124154 fatcat:5m7kno7uzvef3m73cuucg7c5ha

Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric [article]

Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon Brebner
2021 arXiv   pre-print
We propose Blockchain Machine, a hardware accelerator coupled with a hardware-friendly communication protocol, to act as the validator peer.  ...  It can be adapted to applications and their smart contracts, and is targeted for a server with network-attached FPGA acceleration card.  ...  ACKNOWLEDGEMENTS We would like to thank Mercury Systems for providing us the ECDSA verification IP.  ... 
arXiv:2104.06968v2 fatcat:gq427w4phrfkhalytzrheu6c4m

A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device [article]

Santosh Ghosh, Luis S. Kida, Soham Jayesh Desai, Reshma Lal
2020 IACR Cryptology ePrint Archive  
The paper describes the end-to-end scheme to protect communication between an application running inside a SGX enclave and a FPGA accelerator optimized for bandwidth and latency and details the implementation  ...  This paper proposes a method to protect DMA data transfer that can be used to offload computation to an accelerator.  ...  And propose a cryptographic protocol and its hardware implementation in the device that meets the data transfer bandwidth for it on a currently available platform without additional buffering.  ... 
dblp:journals/iacr/GhoshKDL20 fatcat:eadaxsltjbfanpzbmsqblr64jq

Sockets Direct Protocol for Hybrid Network Stacks: A Case Study with iWARP over 10G Ethernet [chapter]

Pavan Balaji, Sitha Bhagvat, Rajeev Thakur, Dhabaleswar K. Panda
2008 Lecture Notes in Computer Science  
together with network hardware accelerators.  ...  Consequently, protocol stacks such as iWARP and MX for 10-Gigabit Ethernet and QLogic InfiniBand, utilize hybrid hardwaresoftware designs that take advantage of the processing power of multicore processors  ...  SDP for Hybrid Hardware-Software Network Stacks As briefly described in Section 2.1, existing designs of SDP have been heavily optimized for hardware offloaded protocol stacks.  ... 
doi:10.1007/978-3-540-89894-8_42 fatcat:h57mrl3fgfctvgoukvjn43yche

Backup Communication Routing Through Internet Satellite, WINDS for Transmitting of Disaster Relief Data

Kohei Arai
2011 International Journal of Advanced Computer Science and Applications  
A countermeasure for round trip delay which occurs in between satellite and ground with network accelerator is investigated together with operating system dependency on effectiveness of accelerator.  ...  Also disaster relief data transmission experiments are conducted for mitigation of disaster together with acceleration of disaster related data transmission between local government and disaster prevention  ...  In order to overcome such influences, hardware accelerator gives a solution. Hardware accelerator allows adjustment of the window size then throughput is recovered in somehow.  ... 
doi:10.14569/ijacsa.2011.020904 fatcat:erz7wpmiuvcqvjwasxxjb5sqku
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