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Geometric programming for circuit optimization

Stephen P. Boyd, Seung Jean Kim
2005 Proceedings of the 2005 international symposium on physical design - ISPD '05  
This tutorial concerns a method for solving a variety of circuit sizing and optimization problems, which is based on formulating the problem as a geometric program (GP), or a generalized geometric program  ...  These nonlinear, constrained optimization problems can be transformed to convex optimization problems, and then solved (globally) very efficiently.  ...  There are many approaches to circuit sizing, including heuristics, and methods based on circuit simulation coupled to a generic numerical optimization method.  ... 
doi:10.1145/1055137.1055148 dblp:conf/ispd/BoydK05 fatcat:4d25sp4fxjhw3bldvq4arfsz2a

On the Circuit Complexity of Neural Networks

Vwani P. Roychowdhury, Alon Orlitsky, Kai-Yeung Siu, Thomas Kailath
1990 Neural Information Processing Systems  
Concluding RenlarksWe have out.lined a new geometric approach for investigating the properties of threshold circuits.  ...  Geometric approaches have proven useful for analyzing threshold gates. An S-input threshold gate corresponds to a hyperpla.ne in n.s.  ... 
dblp:conf/nips/RoychowdhuryOSK90 fatcat:mkuubsyqcfagljwqfpfuzh4lpm

The computational power and complexity of discrete feedforward neural networks

Barbara Borowik, Sophie Laird
2004 Annales UMCS Informatica  
N increases a percentage of threshold functions in relation to the total number of Boolean functions -goes to zero.  ...  This article analyses some aspects of two-and more than two layers of threshold and Boolean circuits (feedforward neural nets), connected with their computational power and node, edge and weight complexity  ...  With regard to analysing threshold gates, especially suitable are geometric approaches, in which an N-input threshold function (gate) corresponds to a hyperplane in .  ... 
dblp:journals/umcs/BorowikL04 fatcat:6uofz7pb25ctxnabiiixc55bum

Quantitative Transformation for Implementation of Adder Circuits in Physical Systems [article]

Jeff Jones, James G.H. Whiting, Andrew Adamatzky
2015 arXiv   pre-print
These gates may be combined to form more complex adding circuits and, ultimately, complete computer systems.  ...  of the full adder circuit, reducing the circuit combinations from a 2:1 mapping to a 1:1 mapping.  ...  In future work it may be possible to apply the approach to more complex circuits and directly pipe the output of one circuit to another in the pipeline without recourse to transforming the values back  ... 
arXiv:1511.05865v1 fatcat:utaphhnsnfd7xnmp4dmhg56f6a

Quantitative transformation for implementation of adder circuits in physical systems

Jeff Jones, James G.H. Whiting, Andrew Adamatzky
2015 Biosystems (Amsterdam. Print)  
In future work it may be possible to apply the approach to more complex circuits and directly pipe the output of one circuit to another in the pipeline without recourse to transforming the values back  ...  The complex 2D spatial arrangement of the adder circuit is, in this example, transformed to a simple 1D chamber.  ... 
doi:10.1016/j.biosystems.2015.05.005 pmid:26007225 fatcat:ggb6kfcptfcclhyf4ubp5rf3om

Analog rank extractors

I.E. Opris
1997 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
In a sorting network approach, the presorting and path combination techniques are used to reduce the rank selector implementation.  ...  This paper focuses on continuous-time analog rank extractors, with an emphasis on MOS circuits.  ...  Neglecting other mismatches in the circuit (threshold offsets and geometric mismatches), the bias current is split equally between all branches.  ... 
doi:10.1109/81.645149 fatcat:jbqahmm3mfcf3b3ml4za4jarse

Towards Quantum Ray Tracing [article]

Luís Paulo Santos and Thomas Bashford-Rogers and João Barbosa and Paul Navrátil
2022 arXiv   pre-print
Through a practical implementation of quantum ray tracing in a 3D environment, we show quantum approaches provide a quadratic improvement in query complexity compared to the equivalent classical approach  ...  Quantum computers have the potential to significantly improve rendering performance through reducing the underlying complexity of the algorithms behind light transport.  ...  We show that compared to a classical approach, quantum algorithms improve the complexity of ray primitive intersection operations.  ... 
arXiv:2204.12797v1 fatcat:pxa2ox2scngftcq7z4adzcshlq

More on the complexity of slice functions

Ingo Wegener
1986 Theoretical Computer Science  
One of the hardest problems in complexity theory seems to be to find a proof that the circuit complexity of some explicitly defined Boolean function is nonlinear in the number of inputs and outputs.  ...  An interesting approach for such a bound is the investigation of slice functions since for these functions circuits over a complete basis, monotone circuits, and the so-called set circuits are nearly equivalent  ...  At present, this new approach seems to give the best chances for a proof of a nonlinear lower bound on the circuit complexity of an explicitly defined Boolean function.  ... 
doi:10.1016/0304-3975(86)90176-3 fatcat:3ieq77rz3zb53l4v5teloaxzny

State space synthesis of integrators based on the MOSFET square law

M.H. Eskiyerli, A.J. Payne, C. Toumazou
1996 Electronics Letters  
If I, = dIJy is to be the geometric mean of two currents: Z , and Zp then Results: To verify its operation, the circuit of Fig. 1 was simulated using HSPICE on a commercial n-wellO.8pn BiCMOS technology  ...  The circuit was then synthesised using the translinear principle. In contrast, Frey [3] followed a more general and rigorous approach.  ... 
doi:10.1049/el:19960383 fatcat:c5wb4l4tvre2vnfkqnmsutcjza

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

M. Stanisavljevic, A. Schmid, Y. Leblebici
2006 The 2006 IEEE International Joint Conference on Neural Network Proceedings  
A benefit of the differential circuit over standard single-ended is shown in case of complex systems.  ...  An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture  ...  On the other hand, the IFA approach has some drawbacks, mainly high computational complexity of used tools, complete dependency on geometrical characteristics and difficulty of handling properly analog  ... 
doi:10.1109/ijcnn.2006.247183 dblp:conf/ijcnn/StanisavljevicSL06 fatcat:siiwdhlosvd4vky3pq722zjcqy

ON THRESHOLD CIRCUITS FOR PARITY [chapter]

Ramamohan Paturi, Michael E. Saks
1990 Colt Proceedings 1990  
The architecture should be able to compute each function in .F for a proper choice of weights. 2.  ...  The architecture should have a minimal number of edges. there are no linear size bounded depth threshold circuits for computing parity. 3. The depth of this architecture should be mini mal.  ...  The technique holds promise towards a complete answer to this trade-off question and also seems to be a natural and a potentially useful approach to the analysis of threshold circuits in general.  ... 
doi:10.1016/b978-1-55860-146-8.50036-9 fatcat:3x3fkwero5deriks2vvqg4jamu

Guest editors' introduction: defect-oriented testing in the deep-submicron era

J. Segura, P. Maxwell
2002 IEEE Design & Test of Computers  
This IC test approach led to parametric test methods focusing on IC parameters other than the logic circuit behavior.  ...  With added constraints of reduced time to market, the complexity of CMOS ICs has grown steadily during the past few decades.  ...  Complexity and economic reasons related to time-to-market pressures have driven this view, and DFT practices that support circuit verification have made today's massive ICs possible.  ... 
doi:10.1109/mdt.2002.1033786 fatcat:pypu7pvts5hexkoo7bsfjy4zbq

Nonlinear relationships in the patterns of neuronal spiking in cortical neurons

R A Chizhenkova, V Y Chernukhin
2000 Journal of biological physics (Print)  
A number of functionswere applied to describe the observed phenomena. On thebasis of regression analysis two populations of corticalneurons with distinct neuronal spiking patterns wereidentified.  ...  number for a burst, meanburst duration) were considered.  ...  The uniform approach to the analysis of spike firing in all recorded neurons was essential to consider different associations of spikes and to summarize results obtained in different units.  ... 
doi:10.1023/a:1005211721101 pmid:23345713 pmcid:PMC3456184 fatcat:pnekwqjdpvfhph7kf2r6yjfr4y

DETERMINATION OF THE COMPLEX PERMITTIVITY VALUES OF PLANAR DIELECTRIC SUBSTRATES BY MEANS OF A MULTIFREQUENCY PSO-BASED TECHNIQUE

Renzo Azaro, Federico Caramanica, Giacomo Oliveri
2009 Progress In Electromagnetics Research M  
The results of some representative experimental tests are shown for a preliminary assessment of the effectiveness of the proposed approach.  ...  Starting from a set of impedance measurements performed on a section of a microstrip transmission line built on the planar dielectric substrate under test, the proposed technique formulates the reconstruction  ...  The two-port circuit is terminated on a short circuit and it is connected to a SMA coaxial connector on the other side, respectively.  ... 
doi:10.2528/pierm09112901 fatcat:bg6dc4vvwfbnpn46lfaac7uxqu

Trading quality for compile time

Yaska Sankar, Jonathan Rose
1999 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99  
This can be used, in conjunction with a routing predictor, to very quickly determine the routability of a given circuit on a given FPGA device.  ...  It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time.  ...  1 We define quality as the wiring area required by the circuit or the speed at which the circuit can operate when mapped to the FPGA.  ... 
doi:10.1145/296399.296449 dblp:conf/fpga/SankarR99 fatcat:onssxr3apffojggnhhrkgdnvqe
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