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A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools

Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi
2008 IPSJ Transactions on System LSI Design Methodology  
For GALS design, we constructed a design flow based on general synchronous design tools, by specification of design constraints and configurations.  ...  Applying the design flow to an experimental multi-core processor GALS design including an asynchronous interconnect based on QDI (Quasi Delay Insensitive) model, we successfully obtained a netlist and  ...  The sequence of C-elements thus forms a data path in the interconnect. With the 1-of-4 encoding, a two-bit data with request is encoded into a four-bit one-hot signal on data paths.  ... 
doi:10.2197/ipsjtsldm.1.58 fatcat:kokffmqglnhlverrjkt2jirrwa

Interconnect Driven Low Power High-Level Synthesis [chapter]

A. Stammermann, D. Helms, M. Schulte, A. Schulz, W. Nebel
2003 Lecture Notes in Computer Science  
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor.  ...  Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RT-level netlists.  ...  Instead, we use Steiner Trees for drawing data transfer wires. To treat the clock distribution network accurately an H-tree (balanced tree) is generated.  ... 
doi:10.1007/978-3-540-39762-5_15 fatcat:2cjvgkfswrbkpgcw4azigfkwha

Timing analysis in high-level synthesis

Kuehlmann, Bergamaschi
1992 IEEE/ACM International Conference on Computer-Aided Design  
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis.  ...  The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach.  ...  Acknowledgements The authors would like to thank Daniel Brand and Louise Trevillyan for the invaluable help in understanding LSS and logic synthesis.  ... 
doi:10.1109/iccad.1992.279348 dblp:conf/iccad/KuehlmannB92 fatcat:o6mee4fxovhtdjnc44adaw6ybq

Architectural Synthesis with Interconnection Cost Control [chapter]

Christophe Jego, Emmanuel Casseau, Eric Martin
2000 IFIP Advances in Information and Communication Technology  
A way to control costly interconnections during the architcctural proccss is prcscnted in this paper.  ...  Keywords: Architectural synthesis tools map algorithms to architectures under various constraints and quickly providc estimations of area and performance.  ...  A way to control and reduce the interconnection cost Architectural synthesis tools are based on a generic architecture model.  ... 
doi:10.1007/978-0-387-35498-9_45 fatcat:4cpglcvadfhdddnboxd3jvnnyy

Synthesis of pipelined DSP accelerators with dynamic scheduling

Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
1995 Proceedings of the 8th international symposium on System synthesis - ISSS '95  
Emphasis will be put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths.  ...  In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units.  ...  Vernalde from IMEC for the constructive remarks during the writing of this paper. The work is also founded on the netlist optimization tools developed by L. Rijnders and Z.  ... 
doi:10.1145/224486.224503 dblp:conf/isss/SchaumontVBM95 fatcat:tddaixxn5fbidboovjlcdjsboy

Concurrent analysis techniques for data path timing optimization

Chuck Monahan, Forrest Brewer
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
Conventional High-level Synthesis techniques create an interconnection structure before physical design.  ...  In this paper we present a set of techniques which analyze the timing trade-offs associated with the position-specific interconnection network given the freedom of high-level binding and rescheduling changes  ...  Problem Specification In this work, the automata based data-path model introduced in [7] is utilized to implicitly execute a series of data flows on a detailed RTL data path.  ... 
doi:10.1145/240518.240527 dblp:conf/dac/MonahanB96 fatcat:brvsqn3fwbcozdcdsescf6odyi

High-level synthesis under multi-cycle interconnect delay

Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi
2001 Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01  
Interconnect delay is now a crucial factor that needs to be considered even during high-level synthesis.  ...  We incorporate the concept of multi-cycle interconnect delay into scheduling and binding process, to reduce the critical path length and therefore the system latency.  ...  Fig. 1 shows a simple centralized architecture model.  ... 
doi:10.1145/370155.370576 dblp:conf/aspdac/JeonKSC01 fatcat:q7ns3o6bbbcntevl7zunxghfpu

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

K. Chakrabarty
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We propose a new synthesis-for-test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system.  ...  This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores.  ...  The synthesis of explicit transparent paths obviates the need for complex data decoding in test generation for microprocessor circuits.  ... 
doi:10.1109/tvlsi.2003.810784 fatcat:2vmmyslctngy7jnmxbnxq2t3zu

Data path tradeoffs using MABAL

Kayhan Küçükçakar, Alice C. Parker
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
The results indicate data path tradeoffs are sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generation or logic synthesis with high-level  ...  synthesis.  ...  Furthermore, if module generators, logic synthesis or logic optimization are employed, their interaction with data-path synthesis procedures must be carefully studied.  ... 
doi:10.1145/123186.123388 dblp:conf/dac/KucukcakarP90 fatcat:resdpapiejcyjbqy6yrhhq4gne

Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA

Lieu My Chuong, Siew-Kei Lam, Thambipillai Srikanthan
2009 2009 IEEE/IFIP International Symposium on Rapid System Prototyping  
In order to accurately predict the delay of the design after place and route, we introduce a new metric for the estimation that models the criticality of the design's interconnectivity.  ...  Experimental results based on a set of embedded functions show that the proposed area estimation can achieve comparable results with the synthesis results of a commercial FPGA tool in the order of milliseconds  ...  In this paper, we focus on area-time estimation for the data-path only. Fig. 3.2.  ... 
doi:10.1109/rsp.2009.15 dblp:conf/rsp/ChuongLS09 fatcat:f3zvdvjtrjav7hstzbktsv7wba

Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis

S. Gupta, N. Savoiu, N. Dutt, R. Gupta, A. Nicolau
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This leads to a need for high-level and compiler transformations that overcome the effects of syntactic variance or programming style on the quality of generated circuits.  ...  These code transformations and controller optimizations have been implemented in a high-level synthesis research framework called Spark, which takes a behavioral description in ANSI-C as input and generates  ...  [24] present an integer-programming model for simultaneous scheduling and allocation that minimizes interconnect. Mujumdar et al.  ... 
doi:10.1109/tcad.2003.822105 fatcat:hjsxg6evmjhjvfchql5aeggxbi

Algorithms for hardware allocation in data path synthesis

S. Devadas, A.R. Newton
1989 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
New algorithms for the simultaneous costlresource constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed.  ...  The most creative step in synthesizing data paths executing software descriptions is the hardware allocation process.  ...  Ma for several interesting discussions on data path synthesis.  ... 
doi:10.1109/43.31534 fatcat:uwsh64ghqzh2robg5dmpd7u7dq

A methodology for synthesis of data path circuits

A. Chowdhary, R.K. Gupta
2002 IEEE Design & Test of Computers  
Acknowledgments We thank Sudhakar Kale, Bobby Wong, Kanchana Sridhar, and William Lock, from Intel, for helping us develop a data path synthesis system based on the methodology presented here.  ...  We also thank Naresh Sehgal, Phani Saripella, Tim Chan, Unni Narayanan, and Tim Ellerbruch, also from Intel, for their support.  ...  We have developed a new methodology for fast, efficient synthesis of data path circuits.  ... 
doi:10.1109/mdt.2002.1047748 fatcat:cjgri6arnzdrhkjwnp4q7m7dxy

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis

R. Karri, B. Iyer, I. Koren
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper we present an area-efficient register transfer level technique for gracefully degradable data path synthesis called phantom redundancy.  ...  There is a tight interdependence between reconfiguration of a (faulty) data path and scheduling and operation-to-operator binding tasks during register transfer level synthesis.  ...  Figure 5 : 5 (a) Hardware model for basic data path synthesis. (b) Hardware model for gracefully degradable data path synthesis using phantom redundancy.  ... 
doi:10.1109/tcad.2002.800450 fatcat:cx4737dt5nh6nhgcxx7lv4cgyq

Methods and tools for high and system level synthesis [chapter]

A. Prihozhy
1997 VLSI: Integrated Systems on Silicon  
This paper presents new methods for high-and system-level synthesis based on transformation of a behavioral description to a special behavioral model, development of new and modification of existing synthesis  ...  techniques for this model, development of net-based synthesis model and techniques extending target architectures.  ...  • generating the data path (DP) and finite state machine (FSM).  ... 
doi:10.1007/978-0-387-35311-1_40 fatcat:kwcngyacyba6ni34sgjiggotly
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