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A robust message passing based stereo matching kernel via system-level error resiliency
2014
2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
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Previously, algorithmic noise tolerance (ANT) has been applied at the arithmetic level of the reparameterize unit and showed greatly enhanced robustness of message passing inference based architectures ...
In this paper, we present an error resilient Markov random field (MRF) message passing based stereo matching hardware (HW) architecture. ...
Two-step (reparameterize, REPARAM, and update message, UPDMSG) message passing algorithm is accelerated in an FPGA, where its data path is fully pipelined and MRF data (unary/smoothness cost) is streamed ...
doi:10.1109/icassp.2014.6855226
dblp:conf/icassp/KimCSR14
fatcat:7mlkxm6tcreupb7g6ldax3qgyi
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
2009
IEEE Transactions on Communications
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Design of LDPC Decoders for Improved Low Error Rate Performance In the past several decades, tremendous progress has been made in both communication theory and practical implementation of communication ...
Then, a reweighted message-passing algorithm is proposed to eliminate local minima caused by the remaining dominant errors. ...
If the absorbing region shrinks after post-processing, it is a good indication that the reweighted message passing algorithm is successful. ...
doi:10.1109/tcomm.2009.11.080105
fatcat:nokjs4c6rbddnp6nijzkmuhulu
Graph Processing on FPGAs: Taxonomy, Survey, Challenges
[article]
2019
arXiv
pre-print
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This is reflected by the recent interest in developing various graph algorithms and graph processing frameworks on FPGAs. ...
Field Programmable Gate Arrays (FPGAs) can be an energy-efficient solution to deliver specialized hardware for graph processing. ...
This problem is solved with the Tree-Reweighted Message Passing (TRW-S) algorithm [113] . Finally, one work considers spreading activation [82] . ...
arXiv:1903.06697v3
fatcat:f5usapd45jgqpf7ynlz4w6e4si
2020 Index IEEE Transactions on Circuits and Systems for Video Technology Vol. 30
2020
IEEE transactions on circuits and systems for video technology (Print)
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., see Sepas-Moghaddam, A., TCSVT Dec. 2020 4496-4512 Hassanpour, H., see Khosravi, M.H., TCSVT Jan. 2020 48-58 Hatzinakos, D., see 2900-2916 Hayat, M., see 2900-2916 He, C., Hu, Y., Chen, Y., Fan ...
., +, TCSVT Nov. 2020 4284-4298
VLSI Architecture for Enhanced Approximate Message Passing Algorithm. ...
Damian, C., +, TCSVT
Aug. 2020 2517-2523
VLSI Architecture for Enhanced Approximate Message Passing Algorithm. ...
doi:10.1109/tcsvt.2020.3043861
fatcat:s6z4wzp45vfflphgfcxh6x7npu
A Survey on Spark Ecosystem for Big Data Processing
[article]
2018
arXiv
pre-print
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Finally, we make a discussion on the open issues and challenges for large-scale in-memory data processing with Spark. ...
Moreover, we also introduce various data management and processing systems, machine learning algorithms and applications supported by Spark. ...
KeystoneML [134] is a framework for ML pipelines, written in Scala, from the UC Berkeley AMPLab designed to simplify the construction of large scale, end-toend, machine learning pipelines with Apache ...
arXiv:1811.08834v1
fatcat:6fxvg6me7rayzm4suoabyg7fii
Brain-Inspired Hardware Solutions for Inference in Bayesian Networks
2021
Frontiers in Neuroscience
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Several stochastic computing architectures using Bayesian stochastic variables have been proposed, from FPGA-like architectures to brain-inspired architectures such as crossbar arrays. ...
., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required ...
The stereo task has been modeled as statistical inference on an MRF model and shows how to implement streaming tree-reweighted message-passing style inference at video rates. ...
doi:10.3389/fnins.2021.728086
pmid:34924925
pmcid:PMC8677599
fatcat:tihogzl6tfbpjdybwpggllwd5u
2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67
2020
IEEE Transactions on Circuits and Systems - II - Express Briefs
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for Adaptive Filtering; TCSII Oct. 2020 2229-2233 Qian, J., Lu, M., and Huang, N., Radar and Communication Co-Existence Design Based on Mutual Information Optimization; TCSII Dec. 2020 3577-3581 Qian ...
Islam, S., see 1464-1468 Ismail, A., and Sandell, M., A Novel Dynamic Detection for Flash Memory; 600-604 Issakov, V., see Aguilar, E., TCSII May 2020 906-910 Iu, H.H., see Lai, Q., 1129-1133 Iu, ...
., +, TCSII May 2020 961-965
Dismantling and Vertex Cover of Network Through Message Passing. ...
doi:10.1109/tcsii.2020.3047305
fatcat:ifjzekeyczfrbp5b7wrzandm7e
Design of large polyphase filters in the Quadratic Residue Number System
2010
2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers
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Specifically, we propose a message-passing and clustering-based organization with a pipelined VFP controller design to meet the scalability, power and performance constraints. ...
with quantized message passing. ...
doi:10.1109/acssc.2010.5757589
fatcat:ccxnu5owr5fyrcjcqukumerueq
Autonomous Driving with Deep Learning: A Survey of State-of-Art Technologies
[article]
2020
arXiv
pre-print
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This is a survey of autonomous driving technologies with deep learning methods. ...
in the crowd through a message passing mechanism. ...
generalizes traditional deep layerby-layer convolutions to slice-by-slice convolutions within feature maps, thus enabling message passing between pixels across rows and columns in a layer. ...
arXiv:2006.06091v3
fatcat:nhdgivmtrzcarp463xzqvnxlwq
OUP accepted manuscript
2019
Progress of Theoretical and Experimental Physics
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Acknowledgements We thank KEK and J-PARC, Japan for their support of infrastructure and the operation of COMET. This work is supported in part by: the Japan Society for the Promotion of Science ( ...
FPGA firmware design A modern FPGA design, Artix-7 (XC7A200T-2FBG676C, Xilinx), is used on the ROESTI board. ...
The logic for the combination algorithm resides in the FPGA on the COTTRI MB. 12 COTTRI FE boards will be required to process the CTH signals. ...
doi:10.1093/ptep/ptz125
fatcat:jajort2e3fhurlgtxgfcyxkjfe
COMET Phase-I Technical Design Report
[article]
2019
arXiv
pre-print
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2018 pre-print arXiv:1812.09018v1 fatcat:4rkbpjiigbappjrf67fhptqci4Other Versions
The Technical Design for the COMET Phase-I experiment is presented in this paper. ...
The experimental sensitivity goal for this process in the Phase-I experiment is 3.1×10^-15, or 90 7× 10^-15, which is a factor of 100 improvement over the existing limit. ...
Acknowledgements We thank KEK and J-PARC, Japan for their support of infrastructure and the operation of COMET. This work is supported in part by: Japan Society for the Promotion of Science ( ...
arXiv:1812.09018v2
fatcat:ghkbedcu3bebpdrmsizof77hv4
2020 Index IEEE Transactions on Instrumentation and Measurement Vol. 69
2020
IEEE Transactions on Instrumentation and Measurement
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Instrumentation Applications; TIM April 2020 1519-1529 Heo, S., see Jung, J.H., TIM Oct. 2020 7530-7541 Hernandez, A., see Aparicio-Esteve, E., TIM Aug. 2020 5589-5603 Hernandez, H., de Souza Sanches ...
Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR TIM Nov. 2020 9262-9271 Helsen, J., see Huchel, L., TIM July 2020 4145-4153 Hemavathi, N., ...
., +, TIM Oct. 2020 8344-8351 Low-pass filters A 1.5-bit DFT Analyzer. ...
doi:10.1109/tim.2020.3042348
fatcat:a5f4fsqs45fbbetre6zwsg3dly
2020 Index IEEE Transactions on Industrial Informatics Vol. 16
2020
IEEE Transactions on Industrial Informatics
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Forests-Based Model for Ultra-Short-Term Prediction of PV Characteristics; TII Jan. 2020 202-214 Imran, A., see Hussain, B., TII Aug. 2020 4986-4996 Imran, M., see Fu, S., TII Sept. 2020 6013-6022 ...
Jiang, C., see Qin, Y., TII Jan. 2020 238-247 Jiang, H., see Ruan, J., 1296-1309 Jiang, H., Ren, J., Lui, J.C.S., and Dustdar, S., Guest Editorial:Special Section on End-Edge-Cloud Orchestrated Algorithms ...
., +, TII Sept. 2020 6124-6132 Logic design FPGA-Based Design for Real-Time Crack Detection Based on Particle Filter. ...
doi:10.1109/tii.2021.3053362
fatcat:blfvdtsc3fdstnk6qoaazskd3i
Rapid SoC Design: On Architectures, Methodologies and Frameworks
[article]
2021
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This increase in complexity in turn leads to an increase in design effort and validation time for hardware and the accompanying software stacks. ...
While the GPU serves as a classical example, accelerators for machine learning, approximate computing, graph processing, and database applications have become commonplace. ...
Prior to the detailed routing, TritonRoute preprocesses the global routing solution using a fast approximation algorithm [55] to ensure a Steiner tree structure for each net. ...
doi:10.7302/1546
fatcat:hekqywqyznaihaisver5be4t4y
The First CHIME/FRB Fast Radio Burst Catalog
[article]
2021
arXiv
pre-print
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Through injection of simulated events into our detection pipeline, we perform an absolute calibration of selection effects to account for systematic biases. ...
We infer a power-law index for the cumulative fluence distribution of α=-1.40±0.11(stat.)^+0.06_-0.09(sys.), consistent with the -3/2 expectation for a non-evolving population in Euclidean space. ...
CHIME is funded by a grant from the Canada Foundation for Innovation (CFI) 2012 Leading Edge Fund (Project 31170) and by contributions from the provinces of British Columbia, Québec and Ontario. ...
arXiv:2106.04352v2
fatcat:xfadvssw4fetraeynl3mgwuyw4
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