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Phase Change and Magnetic Memories for Solid-State Drive Applications

Cristian Zambelli, Gabriele Navarro, Veronique Sousa, Ioan Lucian Prejbeanu, Luca Perniola
2017 Proceedings of the IEEE  
However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck  ...  The state-of-the-art Solid State Drives now heterogeneously integrate NAND Flash and DRAM memories to partially hide the limitation of the non-volatile memory technology.  ...  The advent of three-dimensionally integrated NAND Flash (i.e., 3D NAND) [10] seemed to alleviate such a trade-off, but not the need for the DRAM to cope with the performance disparity between the host  ... 
doi:10.1109/jproc.2017.2710217 fatcat:fof3pr2ixjfqdd3f226s4qqh7e

Applications of Multi-Terminal Memristive Devices: A Review

D. Sacchetto, P. Gaillardon, M. Zervas, S. Carrara, G. De Micheli, Y. Leblebici
2013 IEEE Circuits and Systems Magazine  
Finally, the multi-terminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid CMOS co-fabrication with a CMOS-compatible process.  ...  Moreover, a Generic Memory Structure (GMS) utilizing two ReRAMs for 3D-FPGA is discussed.  ...  Puppo for her help with the bio-memristive nanowires. Moreover, the authors thank the CMI staff of EPFL for help with the fabrication. This work has been partially supported by the Swiss NSF  ... 
doi:10.1109/mcas.2013.2256258 fatcat:lt2kz55cfba6tk7hxnmbi5awwu

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
Kogge, Editor and Study Lead University of Notre Dame May 1, 2008. iii This page intentionally left blank. iv 4  ...  The work was sponsored by DARPA IPTO with Dr. William Harrod as Program Manager, under AFRL contract #FA8650-07-C-7724.  ...  There are currently at least three different classes [86] of such die-level interconnect patterns, Figure 4 .1: 28 • Hierarchical: where cores share multi-level caches in a tree-like fashion, with  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m

D5.1: Market and Technology Watch Report Year 1

Jean-Philippe Nominé
2016 Zenodo  
It is thus the continuation of a well-established effort, using assessment of the HPC market based on market surveys, supercomputing conferences, and exchanges with vendors and between experts involved  ...  It aims at delivering information and guidance useful for decision makers at different levels.  ...  D5.1 Market and Technology Watch Report Year 1 NAND flash NAND flash memories do have a growing market with revenues exceeding USD 25 billion in 2012 [59] .  ... 
doi:10.5281/zenodo.6801690 fatcat:zpnjoenqkvb2te74rvci326vba

D5.2: Market and Technology Watch Report Year 2

Ioannis Liabotis
2017 Zenodo  
It is thus the continuation of a well-established effort, using assessment of the HPC market, including storage, based on market surveys, supercomputing conferences, and exchanges with vendors and between  ...  It aims at delivering information and guidance useful for decision makers at different levels.  ...  is involved in storing data allowing for higher memory density. • 1,000 times lower latency and exponentially greater endurance than NAND • 10 times denser than DRAM • Based on a three-dimensional arrangement  ... 
doi:10.5281/zenodo.6801691 fatcat:jfhjlhwi5fbanmb7xml7rfrhpu

D5.3: Updated Best Practices for HPC Procurement and Infrastructure

Andreas Johansson
2014 Zenodo  
Task 1 – Assessment of petascale systems – has performed a continuous market watch and analysis of trends in petascale HPC systems worldwide.  ...  Specific areas of interest are analysed in depth in terms of the market they belong to and the general HPC landscape, with a particular emphasis on the European point of view.  ...  The partnership is completed with QUANTECH, an SME specialised in the development and marketing of simulation software for industrial forming processes.  ... 
doi:10.5281/zenodo.6572433 fatcat:cwiqrgf33jajjjvhubky4f6rau

D8.3.2: Final technical report and architecture proposal

Ramnath Sai Sagar, Jesus Labarta, Aad van der Steen, Iris Christadler, Herbert Huber
2010 Zenodo  
The document also suggests potential architectures for future machines, the level of performance we should expect and areas where research efforts should be dedicated.  ...  These drives are designed using the latest-generation native SATA interface with an advanced architecture employing 10 parallel NAND flash channels equipped with single-level cell NAND flash memory.  ...  The four cores on a chip contribute a factor of 4× to the performance with 2 chips in a node; doubling the performance per node to 14 GFlop/s.  ... 
doi:10.5281/zenodo.6546134 fatcat:35eigjqrzvb3vfd3pjud2oswtu

Towards Oxide Electronics: a Roadmap

M. Coll, J. Fontcuberta, M. Althammer, M. Bibes, H. Boschker, A. Calleja, G. Cheng, M. Cuoco, R. Dittmann, B. Dkhil, I. El Baggari, M. Fanciulli (+44 others)
2019 Applied Surface Science  
Abstract A magnetic tunnel junction (MTJ) with a ferromagnet (FM)/oxide/ FM trilayer structure is an indispensable spintronic device for magnetic read sensors in hard disk drives and magnetic memory cells  ...  Ferroelectric oxides are already used in polycrystalline form in commercial memories and can soon have a great impact with improved optical devices and new ferroelectric memories.  ...  This work is part of the BioWings project which has received funding from the European Union's Horizon 2020 under the Future and Emerging Technologies (FET) programme with a grant agreement No. 801267.  ... 
doi:10.1016/j.apsusc.2019.03.312 fatcat:3rqm2kwuv5gk3dpmb4sv7mg6ui

T2K ND280 Upgrade – Technical Design Report [article]

K.Abe, H.Aihara, A.Ajmi, C.Andreopoulos, M.Antonova, S.Aoki, Y.Asada, Y.Ashida, A.Atherton, E.Atkin, D.Attié, S.Ban (+372 others)
2020 arXiv   pre-print
of predicted events at Super-Kamiokande is reduced to about 4%.  ...  The goal of this upgrade is to improve the Near Detector performance to measure the neutrino interaction rate and to constrain the neutrino interaction cross-sections so that the uncertainty in the number  ...  The module incorporates up to 1 GB of DDR3 memory, 512 MB of NAND flash, offers more than 150 user I/O pins and 4-8 multi-gigabit per second capable transceivers.  ... 
arXiv:1901.03750v2 fatcat:3srd7gvm3zhrjjhskt4wmaduma

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin
2016
For example, using 4 kB SRAM banks, a multi-core architecture with 8 processing units comprises 64 kB of tightly-coupled, shared data memory.  ...  Figure 3 . 16 - 316 Multi-core architecture with shared instruction and data memories, each connected over a crossbar with broadcast support.  ... 
doi:10.5075/epfl-thesis-7168 fatcat:qqbipezpknhstkk3o2t5mwjvbi

On Multicast in Asynchronous Networks-on-Chip: Techniques, Architectures, and FPGA Implementation

Kshitij Bhardwaj
2018
The consumer electronics market is replete with many-core systems in the range of 16 cores to thousands of cores on chip, integrating multi-billion transistors.  ...  Moreover, NoCs are a natural match with asynchronous design techniques, as they separate communication infrastructure and timing from the computational elements.  ...  These high-performance FPGAs used fine-grain bit-level pipelining, and could operate at 1.5 GHz in 22 nm technology.  ... 
doi:10.7916/d81279jk fatcat:6a3x3ebbzfgq5kyigtxyt4uhly

Design of a flexible data path for heterogenous coarse-grain reconfigurable logic circuits

Martin Johann Schmölzer, Christoph Grimm, Florian Schupfer, Johann Glaser
2014
Based on the 'Finite State Machine with Data Path' model, which forms the basis for high level synthesis, a highly flexible corase-grain reconfi gurable digital circuit architecture, consisting of recon  ...  Anhand des der High-Level-Synthese zugrundeliegenden 'Finite State Machine with Data Path' - Modells wurde eine rekon gurierbare Schaltungsarchitektur entwickelt, die eine möglichst hohe Flexibilität in  ...  Figure 4 . 4 Figure 4.13: Content Addressable Memory cell Figure 4 . 4 Figure 4.14 shows the structure of the D Flip-Flop cell.  ... 
doi:10.34726/hss.2014.23586 fatcat:2gkqi7hb7jfxxczklcoiboxmty

GPU accelerated onboard data processing for downlink optimisation

Rebecca Davidson
2019
The dimensionality and volume of raw payload data generated onboard Earth Observation (EO) satellites has increased beyond the capabilities of satellite downlink technologies, as a result a bottleneck  ...  As a result, a new onboard satellite data processing architecture is proposed.  ...  structures such as shared memory and global memory.  ... 
doi:10.15126/thesis.00852470 fatcat:napelwugefei7pmh3txxtg4rr4

Towards Oxide Electronics: a Roadmap [article]

M. Coll, J. Fontcuberta, M. Althammer, M. Bibes, H. Boschker, A. Calleja, G. Cheng, M. Cuoco, R. Dittmann, B. Dkhil, I. El Baggari, M. Fanciulli (+45 others)
2020
This work is part of the BioWings project which has received funding from the European Union's Horizon 2020 under the Future and Emerging Technologies (FET) programme with a grant agreement No. 801267.  ...  Acknowledgements Author thanks fruitful discussions with Dr. J. Santiso.  ...  magnetic random access memory (STT-MRAM) and NAND-Flash.  ... 
doi:10.34657/3597 fatcat:2w75pizz7bfo7bywgkpcevn43i