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A framework for statistical modeling of superscalar processor performance

D.B. Noonburg, J.P. Shen
Proceedings Third International Symposium on High-Performance Computer Architecture  
This dissertation presents a statistical approach to modeling superscalar processor performance.  ...  Instead of directly modeling an execution trace, as with standard simulationbased performance models, a statistical model works with the probabilities of instruction types, instruction sequences, and processor  ...  Contributions Statistical Modeling Framework The key contribution of this research is a framework for statistical processor performance modeling.  ... 
doi:10.1109/hpca.1997.569691 dblp:conf/hpca/NoonburgS97 fatcat:jtubckj4uvd4riogmbaneyei5m

Automated design of application specific superscalar processors

Tejas S. Karkhanis, James E. Smith
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Analytical modeling is applied to the automated design of application-specific superscalar processors.  ...  The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area.  ...  We also thank Lieven Eeckhout, Stijn Eyerman, and anonymous reviewers for numerous suggestions that improved this work.  ... 
doi:10.1145/1250662.1250712 dblp:conf/isca/KarkhanisS07 fatcat:pmvkhmofira2rjnkj46lboxfl4

Automated design of application specific superscalar processors

Tejas S. Karkhanis, James E. Smith
2007 SIGARCH Computer Architecture News  
Analytical modeling is applied to the automated design of application-specific superscalar processors.  ...  The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area.  ...  We also thank Lieven Eeckhout, Stijn Eyerman, and anonymous reviewers for numerous suggestions that improved this work.  ... 
doi:10.1145/1273440.1250712 fatcat:7apekedwtvf5zbkyvbbdb6expa

A mechanistic performance model for superscalar in-order processors

Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout
2012 2012 IEEE International Symposium on Performance Analysis of Systems & Software  
Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors.  ...  The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch  ...  Acknowledgements We thank the reviewers for their constructive and insightful feedback. Stijn Eyerman is supported through a postdoctoral fellowship by the Research Foundation-Flanders (FWO).  ... 
doi:10.1109/ispass.2012.6189202 dblp:conf/ispass/BreugheEE12 fatcat:pdnulftpozcgve4z6efauw7qnm

Accurately approximating superscalar processor performance from traces

Kiyeon Lee, Shayne Evans, Sangyeun Cho
2009 2009 IEEE International Symposium on Performance Analysis of Systems and Software  
Trace-driven simulation of superscalar processors is particularly complicated.  ...  Our work forms a basis for fast, accurate, and configurable multicore processor simulation using a pre-determined processor core design.  ...  The authors thank the anonymous reviewers for their constructive comments.  ... 
doi:10.1109/ispass.2009.4919655 dblp:conf/ispass/LeeEC09 fatcat:hhq4ihnt7jd63dscz3b7xwh7ky

Statistical simulation: Adding efficiency to the computer designer's toolbox

L. Eeckhout, S. Nussbaum, J.E. Smith, K. De Bosschere
2003 IEEE Micro  
Similarly, for making system-level design decisions, where a processor (or several processors) might be combined with many other components, a very detailed simulation model is often unjustified or impractical  ...  These benchmarks can each contain billions of dynamically executed instructions, and typical simulators run many orders of magnitude slower than real processors, producing a relatively long runtime for  ...  Acknowledgments Lieven Eeckhout is a postdoctoral fellow of the Fund for Scientific Research-Flanders (Belgium; F.W.O. Vlaanderen). James E.  ... 
doi:10.1109/mm.2003.1240210 fatcat:nith3o67vvcrjlvxg77wvqyzh4

An Instruction Throughput Model of Superscalar Processors

Tarek M. Taha, Scott Wills
2008 IEEE transactions on computers  
The model presented in this paper facilitates a rapid exploration of the architecture design space for superscalar processors.  ...  The model calculates the instruction throughput of superscalar processors using a set of key architecture and application properties. It was validated with the Simplescalar out-of-order simulator.  ...  [13] derived superscalar processor models based on queuing theory. Michaud et. al. [14] developed a simple leaky bucket model of superscalar processor performance.  ... 
doi:10.1109/tc.2007.70817 fatcat:kvve7lclabdivloufwkxvsuopa

Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance

Maximilien B. Breugh, Stijn Eyerman, Lieven Eeckhout
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5  ...  We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target;  ...  ACKNOWLEDGMENTS We thank the associate editor and the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/2678277 fatcat:cvx44nejindk7k2giqn6bafjxa

A Predictive Performance Model for Superscalar Processors

P. Joseph, Kapil Vaswani, Matthew Thazhuthaveetil
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across processor design space using  ...  We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters  ...  Experimental Framework The accuracy of our model construction depends on the accuracy of the simulator. Hence, we use a detailed and validated superscalar processor simulator in our experimentation.  ... 
doi:10.1109/micro.2006.6 dblp:conf/micro/JosephVT06 fatcat:s653vjt32jdlthcfeq4iystbhy

High-level modeling and FPGA prototyping of microprocessors

Joydeep Ray, James C. Hoe
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper presents a case study in developing the synthesizable high-level model of a superscalar processor and producing a working prototype in FPGA.  ...  Using an experimental operation-centric hardware description language, we have created the synthesizable model of a superscalar speculative out-of-order core for the integer subset of SimpleScalar PISA  ...  The processor models include performance counters that can be defined or reassigned, from run to run, to collect different statistics and to increase the observability of run-time hardware behaviors.  ... 
doi:10.1145/611817.611833 dblp:conf/fpga/RayH03 fatcat:yixqwuqjyfg7veojoytnwyoudu

High-level modeling and FPGA prototyping of microprocessors

Joydeep Ray, James C. Hoe
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
This paper presents a case study in developing the synthesizable high-level model of a superscalar processor and producing a working prototype in FPGA.  ...  Using an experimental operation-centric hardware description language, we have created the synthesizable model of a superscalar speculative out-of-order core for the integer subset of SimpleScalar PISA  ...  The processor models include performance counters that can be defined or reassigned, from run to run, to collect different statistics and to increase the observability of run-time hardware behaviors.  ... 
doi:10.1145/611831.611833 fatcat:z6lfmr4aungeljvp77o42jzzha

A Visual Simulation Framework For Simultaneous Multithreading Architectures

Adrian Florea, Alexandru Ratiu, Arpad Gellert, Lucian N. Vintan
2011 ECMS 2011 Proceedings edited by: T. Burczynski, J. Kolodziej, A. Byrski, M. Carvalho  
We introduce the SMTAHSim framework, an educational tool that simulates in an interactive manner the important aspects of this particular microarchitecture.  ...  This paper aims to make a suggestive description of the concepts and principles implemented into a Simultaneous Multithreading Architecture.  ...  The framework came with some basic configurations which allow a proper evaluation of the SMT architecture's performances.  ... 
doi:10.7148/2011-0403-0409 dblp:conf/ecms/FloreaRGV11 fatcat:ju5njgpyxbbgzhrwea5teffrla

Criticality-driven superscalar design space exploration

Sandeep Navada, Niket K. Choudhary, Eric Rotenberg
2010 Proceedings of the 19th international conference on Parallel architectures and compilation techniques - PACT '10  
For the DSE of superscalar processors on SPEC 2000 benchmarks, on average, criticality-driven walk achieves 3.8x speedup over random walk and criticality-driven simulated annealing achieves 2.3x speedup  ...  Criticality analysis at a given design point provides a localized view of the region around the design point without performing simulations at the neighboring points.  ...  ACKNOWLEDGMENTS We would like to thank the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/1854273.1854308 dblp:conf/IEEEpact/NavadaCR10 fatcat:dvijbjiob5filpv4pudnugfsa4

The optimum pipeline depth for a microprocessor

A. Hartstein, Thomas R. Puzak
2002 SIGARCH Computer Architecture News  
These results are explored across a wide range of superscalar processors, both in-order and out-of-order.  ...  The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation.  ...  Davidson for many stimulating discussions and helpful comments on this work.  ... 
doi:10.1145/545214.545217 fatcat:zqmd75l6tzee3pj3cyxuccztge

Enabling HMMER for the Grid with COMP Superscalar

Enric Tejedor, Rosa M. Badia, Romina Royo, Josep L. Gelpí
2010 Procedia Computer Science  
Although performance is not a main objective of this work, we also present some test results where COMP Superscalar, using a new pre-scheduling technique, clearly outperforms a well-known parallelization  ...  In particular, we present a sequential version of the HMMER hmmpfam tool that, when run with COMP Superscalar, is decomposed into tasks and run on a set of distributed resources, not burdening the programmer  ...  Acknowledgment The authors gratefully acknowledge the financial support of the Comisión Interministerial de Ciencia y Tecnología (CICYT, Contract TIN2007-60625), the Generalitat de Catalunya (2009-SGR-  ... 
doi:10.1016/j.procs.2010.04.296 fatcat:2vudddibevfbrkftpg46wuilpq
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