81,257 Hits in 3.4 sec

A constraint logic programming framework for the synthesis of fault-tolerant schedules for distributed embedded systems

Kare Harbo Poulsen, Paul Pop, Viacheslav Izosimov
2007 2007 IEEE Conference on Emerging Technologies & Factory Automation (EFTA 2007)  
We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures.  ...  We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults.  ...  In this paper we propose a CLP framework for producing fault-tolerant schedules such that the application is schedulable in the presence of transient faults, and the constraints and tradeoffs imposed by  ... 
doi:10.1109/efta.2007.4416850 dblp:conf/etfa/PoulsenPI07 fatcat:5rywqwvayzgxnafrkb7eznlqyu

A framework for scheduler synthesis

K. Altisen, G. Gossler, A. Pnueli, J. Sifakis, S. Tripakis, S. Yovine
Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054)  
The framework. Description formalism Semantic model Synchronization modes A system of three tasks A robotic arm Figure 2 . 2 Example of two jobs.  ...  Greeting card specification translated into a TAD. Controller obtained by synthesis. Figure 12 . 12 A system with three tasks. Figure 13 .Figure 14 . 1314 PND of the system with three tasks.  ... 
doi:10.1109/real.1999.818838 dblp:conf/rtss/AltisenGPSTY99 fatcat:f6x6d32herh2jmamgfzt7iwq4i

A framework for scheduling and context allocation in reconfigurable computing

R. Maestre, M. Fernandez, R. Hermida, N. Bagherzadeh
Proceedings 12th International Symposium on System Synthesis  
This paper describes the different aspects regarding the scheduling problem in a reconfigurable architecture.  ...  We also propose a general strategy in order to perform at compilation time a scheduling that includes all possible optimizations regarding context (configuration) and data transfers.  ...  Figure 2 .Figure 1 . 21 Two extreme cases of execution sequence for a generic application. Framework and M1 chip. Figure 3 . 3 Scheduling within a partition for iteration i: a. Kernel schedule, b.  ... 
doi:10.1109/isss.1999.814272 dblp:conf/isss/MaestreFHB99 fatcat:bt25rplvbnhfrhl7ml7ab2gqti

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding

Xiuyan Zhang, Ouwen Shi, Jian Xu, Shantanu Dutt
We present a power-driven hierarchical framework for module/functional-unit selection, scheduling, and binding in high level synthesis.  ...  Towards this end, we integrate an improved version of the very runtime-efficient list scheduling algorithm called modified list scheduling (MLS) with a power-driven simulated annealing (SA) algorithm for  ...  We also thank the anonymous reviewers for their comments, which have improved the paper.  ... 
doi:10.25417/uic.14721474.v1 fatcat:azsypu4kefbafggcyafoxop6ja

Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems

Florian Sagstetter, Peter Waszecki, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty
2016 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We propose a multi-schedule synthesis approach that determines the common parts of multiple variants and generates a schedule that exploits this commonality.  ...  Hence, a multi-schedule defines individual variant schedules with an identical schedule for applications common to different variants.  ...  This paper proposes a framework for multi-schedule synthesis for variant management.  ... 
doi:10.1109/tcad.2015.2488480 fatcat:6o272rwdlzh6xe45n2hggcqgiq

A digital microfluidic biochip synthesis framework

Daniel Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
We also present and describe a number of highquality 2D and 3D debugging tools that provide graphical output for each stage of synthesis.  ...  We introduce an open source DMFB synthesis framework to encourage collaboration between researchers working in the area.  ...  The framework has also been used to produce new research results, including two new scheduling algorithms [7] [10] and a fast online DMFB synthesis flow that is intended for dynamic interpretation, rather  ... 
doi:10.1109/vlsi-soc.2012.6379026 dblp:conf/vlsi/GrissomOPPDLB12 fatcat:62d4nx3x3ze7nn25ank7ophybm

Poster Abstract: An Optimizing Framework for Real-Time Scheduling

Sakthivel Manikandan Sundharam, Sebastian Altmeyer, Nicolas Navet
2016 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)  
This paper discusses a novel optimization framework which automates the selection and configuration of the scheduling policy.  ...  The system synthesis step involving both analysis and optimization then generates a scheduling solution which at runtime is enforced by the execution environment.  ...  Scheduler Synthesis In this section, we explain the core of the framework, i.e., the scheduler synthesis.  ... 
doi:10.1109/rtas.2016.7461346 dblp:conf/rtas/SundharamAN16 fatcat:7wtfrfx7izhhxchxn23s37psdm

Software synthesis from the dataflow interchange format

Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya
2005 Proceedings of the 2005 workshop on Software and compilers for embedded systems - SCOPES '05  
This framework allows designers to efficiently explore the complex range of implementation trade-offs that are available through various dataflow-based techniques for scheduling and memory management.  ...  Furthermore, the DIF-to-C framework provides a standard, vendor-neutral mechanism for linking coarse grain dataflow optimizations with fine grain hand-optimized libraries and the large body of optimization  ...  DIFtoC Code Generator In the DIF-to-C software synthesis framework, DIFtoC is the base class for performing code generation.  ... 
doi:10.1145/1140389.1140394 dblp:conf/scopes/HsuB05 fatcat:7m4rr2bdwjgk7brhgtdwg4ipiu

Automatic Synthesis and Verification of Real-Time Embedded Software [chapter]

Pao-Ann Hsiung, Shang-Wei Lin
2004 Lecture Notes in Computer Science  
Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software.  ...  In this work, we reveal the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF) 1 , which integrates software component-based  ...  Design Automation: For synthesis, we employ quasi-static and quasidynamic scheduling methods [10] , [11] that generate program schedules for a single processor.  ... 
doi:10.1007/978-3-540-30121-9_2 fatcat:bkmrzrc2c5do3goizu6nxwnfky

Thread warping

Greg Stitt, Frank Vahid
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
We introduce a framework of architecture, CAD tools, and operating system that together support thread warping.  ...  Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and  ...  The synthesis execution times ranged from 22 CONCLUSIONS We introduced a framework for dynamic synthesis of thread accelerators, or thread warping, which transparently creates custom FPGA circuits  ... 
doi:10.1145/1289816.1289841 dblp:conf/codes/StittV07 fatcat:clqzdsg76fedxihf6phlsjcxqm

SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures

Andreas Popp, Andreas Herrholz, Kim Griittner, Yannick Le Moullec, Peter Koch, Wolfgang Nebel
2010 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems  
These cost estimates are fed to a mapping framework to obtain a static binding and schedule for the architectures under exploration.  ...  With the proposed methodology the designer does not have to perform full synthesis and implementation for design space exploration.  ...  To obtain cost estimates for the HW implementation of a task, we use our SystemC/C++ synthesis tool [15] translating the transformed SystemC model to synthesisable RT-level VHDL.  ... 
doi:10.1109/ddecs.2010.5491801 dblp:conf/ddecs/PoppHGMKN10 fatcat:w7f4kqwg7fhghfk6uke3z4tsqq

Frequency-Domain Data-Driven Controller Synthesis for Unstable LPV Systems

Tom Bloemers, Roland Tóth, Tom Oomen
2021 IFAC-PapersOnLine  
Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of  ...  If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User  ...  The paradigm of linear parameter-varying (LPV) systems has been developed to provide a systematic framework for the analysis and design of gain-scheduled controllers for nonlinear systems (Shamma and  ... 
doi:10.1016/j.ifacol.2021.08.589 fatcat:mydqcm3e6jfavdnbhdgaap2bj4

Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis

Rohit Sinha, Hiren D. Patel
2011 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines  
We implement our extensions in a high-level synthesis framework based on the abstract state machine formalism, and we generate synthesizable VHDL.  ...  In doing so, we make the following four contributions: 1) we extend the definition of control data flow graphs (CDFGs) to define timed CDFGs (TCDFGs), 2) we define a scheduling algorithm for timed constructs  ...  For these reasons, we select the FDS scheduling algorithm. III. BACKGROUND: SYNTHESIS FROM ASMS We implement our scheduling back-end as an extension to the SynASM [2] framework.  ... 
doi:10.1109/fccm.2011.49 dblp:conf/fccm/SinhaP11 fatcat:winlknqzxjhozlisq6i6vim6eu

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications

Fabrizio Ferrandi, Vito Giovanni Castellana, Serena Curzel, Pietro Fezzardi, Michele Fiorito, Marco Lattuada, Marco Minutoli, Christian Pilato, Antonino Tumeo
2021 2021 58th ACM/IEEE Design Automation Conference (DAC)  
This paper presents the open-source high-level synthesis (HLS) research framework Bambu.  ...  The integration with synthesis and verification backends (commercial and open-source) allows researchers to quickly test any new finding and easily obtain performance and resource usage metrics for a given  ...  This paper presents the open-source HLS research framework Bambu.  ... 
doi:10.1109/dac18074.2021.9586110 fatcat:vwgjws4mjngszotvrnlbd4ui7y

Developing a new computer music programming language in the 'research through design' context

Hiroki Nishino
2012 Proceedings of the 3rd annual conference on Systems, programming, and applications: software for humanity - SPLASH '12  
We describe our practice in the development of a computer music language from the perspective of the RtD.  ...  Yet, the emerging approach of 'Research through Design (RtD)' in HCI also casts a significant question as to how the academic contribution can be made through the design of such DSLs.  ...  which resulted in a novel abstraction of sound synthesis framework and programming concept for computer music.  ... 
doi:10.1145/2384716.2384736 dblp:conf/oopsla/Nishino12 fatcat:7frfa7zn55fz5ai4hp3dl3kinm
« Previous Showing results 1 — 15 out of 81,257 results