A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
A formal model for defining and classifying delay-insensitive circuits and systems
1986
Distributed computing
Preserved Fulltext
Louis, possible, where I became familiar with delay-insensitive systems and benefited a lot from the approach towards delay-insensitivity that had been established already in his group. ...
of its possible applications to delay-insensitive systems. ...
Trace theory In order to define and classify delay-insensitive circuits we need a formalism for their specification. ...
doi:10.1007/bf01660032
fatcat:bz3staok2febdi57r6uhvabvru
On the delay-sensitivity of gate networks
1992
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Acknowledgement The authors wish to thank Tom Verhoeff and Michael Yoeli for their careful reading of earlier drafts of this paper and for their many constructive suggestions. ...
[2, 8, 15] , quasi delay-insensitive circuits [11] , and self-timed systems [6, 19] . ...
Informally, a delay-insensitive circuit is one whose correctness is insensitive to delays in the wires and primitive elements. ...
doi:10.1109/12.177306
fatcat:aah6nknmzrhlne6eupoqo6wfdu
A self-learning framework to detect the intruded integrated circuits
2016
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
circuits. ...
The cross validation comparison of these learner shows that eager learners are able to detect the intrusion with 96% accuracy and also require less amount of memory and processing power compared to other ...
For example power, delay, current and frequency, of the integrated circuits are used to develop a trained model using RapidMiner studio [16] , which provides software platform for machine learning. ...
doi:10.1109/iscas.2016.7538895
dblp:conf/iscas/LodhiAKHAH16
fatcat:6lw6gkpalff6dnpo6f5t2mry5a
Robust and Energy-Efficient Hardware: The Case for Asynchronous Design
2021
Journal of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. ...
Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes ...
ACKNOWLEDGMENTS This research was partially funded by CAPES and CNPq (grant 312917/2018-0), Brazilian funding organizations. ...
doi:10.29292/jics.v16i2.518
fatcat:3o2fynlz6rgrlg44dkz5jxp4dq
Modeling and design of asynchronous priority arbiters for on-chip communication systems
[chapter]
2002
IFIP Advances in Information and Communication Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. ...
Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. ...
suited to model and synthesize delay-insensitive circuits [2][3] . ...
doi:10.1007/978-0-387-35597-9_27
fatcat:oqowulqvsrft7otpmu7vxj4xni
LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES
2011
Journal of Circuits, Systems and Computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We exploited Dependency Graph model to produce a formal performance analysis. ...
This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Quasi Delay Insensitive asynchronous pipelines while still maintaining high performance of these circuits. ...
Quasi delay insensitive (QDI) circuits are like DI circuits with a weak timing constraint Ref. 13 . ...
doi:10.1142/s0218126611007207
fatcat:44ext2mvrjcfjpigwxqyws3p7e
Modeling and design of asynchronous circuits
1999
Proceedings of the IEEE
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2016; you can also visit the original URL.
The file type is application/pdf.
operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding ...
This technology review explores the behavioral and structural design domains for asynchronous circuits and systems. ...
Table 1 Delay-Insensitive Codes for Input Data (Bits a and b) and Output Data (Bits s and c) of a Half Adder
B. ...
doi:10.1109/5.740017
fatcat:ud3rqhiozja6rkf5prhsnvr35q
Relativistic Causality and Clockless Circuits
2011
ACM Journal on Emerging Technologies in Computing Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Other Versions
The need for a proper model, particularly acute in the design of clockless delay-insensitive (DI) circuits, leads one to reconsider the classical descriptions of time and of the resulting order and causal ...
Time plays a crucial role in the performance of computing systems. ...
The formalization of delay insensitivity (DI) [12, 22, 2, 26] provides a powerful conceptual framework for designing asynchronous circuits. ...
doi:10.1145/2043643.2043650
fatcat:ntfqjcnnrrdylnjoqu33qulh34
Concurrent computing machines and physical space-time
2003
Mathematical Structures in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Using a graphic representation, we show that synchronous and asynchronous circuits reflect the same opposition as the Newtonian and relativistic causal structures for physical space-time. ...
We compare synchronous and asynchronous systems, and make a brief survey of some methods used to deal with computing interferences. ...
Delay-insensitivity provides an interesting transition between local properties, like those defining sequential processors, and global ones, like those exhibited by distributed systems. ...
doi:10.1017/s0960129503004067
fatcat:pjhmed2e4zbmhcig27joeopdzq
The Family of 4-phase Latch Protocols
2008
2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
When equivalence classes are calculated for parallel pipeline behaviours they are dominated by 15 shapes (all of which are delay-insensitive) which are related by a simple lattice. ...
Several published circuits are shown to map to 16 of our 137 family members. ...
Protocol Categories These cut-aways allow us to classify pipeline protocols into three families. The delay-insensitive family consists of both left and right DI cut-aways. ...
doi:10.1109/async.2008.19
dblp:conf/async/BirtwistleS08
fatcat:aefbtg2sfbhyxbkkfwbajcudpy
Elastic Circuits
2009
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. ...
This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. ...
In the asynchronous setting, more detailed models can be defined that capture particular types of delays for a stage of the circuit [56] : function evaluation and reset delay, completion detection delay ...
doi:10.1109/tcad.2009.2030436
fatcat:6anbrdoea5hjhf3gsjp3myxvuq
Model-Based Passive Testing of Safety-Critical Components
[chapter]
2011
Model-Based Testing for Embedded Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
However, a comprehensive theory and taxonomy of methods and techniques for model-based passive testing does -as far as we know-not yet exist and is from today's perspective still very much a topic for ...
the model-based passive testing of a small concurrent system in form of a cellular automaton. ...
Model-based testing of such systems is particularly simple since delay-insensitive circuits are generated from CSP-like specifications. ...
doi:10.1201/b11321-17
fatcat:jipuis6gczdjtk4qbmjkt6v36e
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation
2009
2009 International Conference on Reconfigurable Computing and FPGAs
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection ...
Using a soft-core processor as an example, this paper shows how an off-the-shelf FPGA can be used for asynchronous Four State Logic designs, on which future fault injection experiments will be conducted ...
Finally, there is the group of delay-insensitive circuits for which no timing assumptions are made at all. Gate and wire delays are considered unbounded. ...
doi:10.1109/reconfig.2009.35
dblp:conf/reconfig/JeitlerL09
fatcat:cucl3aylgnemzgm22cfrxsyydy
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design
2008
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is application/pdf.
Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task. ...
Index Terms-Design refinement, formal verification, synchronization, system design. Tarvo Raudvere received the Dipl.Eng. and M.Sc. degrees in computer and system engineering from ...
We classify transformations, which add a delay to a computation block as temporal refinements. ...
doi:10.1109/tcad.2008.923249
fatcat:rmtkirn665gm7fq2ya7fggmwbm
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits
2018
2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asynchrony ...
This paper suggests how an industrial design flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory ...
by the four competitiveness clusters Minalogic, SCS, Systematic Paris-Région, and Derbi, and by the European Community under project "THINGS2DO" of the ENIAC Nanoelectronics Joint Technology Initiative ...
doi:10.1109/async.2018.00021
dblp:conf/async/BouzafourRG0S18
fatcat:kp56s24fkbdrze56f6qy4hiari
« Previous
Showing results 1 — 15 out of 4,203 results