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A Flexible SoC and Its Methodology for Parser-Based Applications

Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki
2016 ACM Transactions on Reconfigurable Technology and Systems  
CONCLUSION In this article, we presented an efficient and flexible SoC architecture performing textbased message analysis for network applications.  ...  To alleviate the burden in hardware-based implementations and increase design flexibility, the codesign methodology proposes to blue split an application based on the required performances.  ...  ELECTRONIC APPENDIX The electronic appendix for this article can be accessed in the ACM Digital Library. Received March 2014; revised July 2014; accepted -  ... 
doi:10.1145/2939379 fatcat:fikk5qyt3jehrodhs4zgptggbq

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms

Shijie Zhou, Weirong Jiang, Viktor K. Prasanna
2014 2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)  
The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches.  ...  Software Defined Networking (SDN) has been proposed as a flexible solution for the next generation Internet provision.  ...  Equipment grant and toolset from Xilinx, Inc. are gratefully acknowledged.  ... 
doi:10.1109/pccc.2014.7017053 dblp:conf/ipccc/ZhouJP14 fatcat:xifho3tnpfdbvcaj6y52ofzf5y

A Survey on Reconfigurable System-on-Chips

Hung Kiem Nguyen, Tu Xuan Tran
2018 REV Journal on Electronics and Communications  
The unique characteristic of such systems is integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip.  ...  Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in  ...  Design-time methodologies (e.g. [12, 44] , and [14] ) are generally aimed at designing the NoC for a specific application.  ... 
doi:10.21553/rev-jec.147 fatcat:zqjzktktbjh4los7luipp45cvy

Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework

Jer-Min Hsiao, Chun-Jen Tsai
2007 2007 IEEE International Symposium on Circuits and Systems  
In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.  ...  In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools.  ...  The RVC framework actually fits the platform-based design principle of SoC quite well. For maximal flexibility, the GCU will be implemented in software and running on the processor core of an SoC.  ... 
doi:10.1109/iscas.2007.377997 dblp:conf/iscas/HsiaoT07 fatcat:iswdystrrbaqlpicm4f4xtzy34

Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices

Yassine Aoudni, Guy Gogniat, Mohamed Abid, Jean-Luc Philippe
2006 2006 International Conference on Microelectronics  
The instruction granularity consists in linking integration process in reconfigurable SoC based on NIOSII custom hardware with the main registers of processor core and a processor core. 3D synthesis application  ...  For this reason, the use of video, and networking applications.  ...  The instruction granularity consists in linking integration process in reconfigurable SoC based on NIOSII custom hardware with the main registers of processor core and a processor core. 3D synthesis application  ... 
doi:10.1109/icm.2006.373284 fatcat:wjhslqgydnbm7cods2l3htghny

PhasorSec: Protocol Security Filters for Wide Area Measurement Systems

Prashant Anantharaman, Kartik Palani, Rafael Brantley, Galen Brown, Sergey Bratus, Sean W. Smith
2018 2018 IEEE International Conference on Communications, Control, and Computing Technologies for Smart Grids (SmartGridComm)  
The strict availability and timing requirements of the grid make it critical that input validation be done right and in a timely fashion.  ...  PhasorSec is a hardened security filter for the synchrophasor communication protocol, C37.118.  ...  Carl Hauser and Tim Yardley for their help and guidance in obtaining datasets for our research.  ... 
doi:10.1109/smartgridcomm.2018.8587501 dblp:conf/smartgridcomm/AnantharamanPBB18 fatcat:6ap2f6utsre47nkmwblzvk52yy

Wrapping of Soft IPs for Interface‐based Design Using Heterogeneous Metaprogramming

Robertas Damaševičius, Vytautas Štuikys
2003 Informatica  
Heterogeneous MPG is based on the simultaneous usage of a domain language for describing domain functionality and a metalanguage for developing generic components and program generators.  ...  We present a design framework based on the MPG techniques.  ...  Acknowledgements We would like to thank the anonymous referees for their insightful comments and suggestions for improving the paper.  ... 
doi:10.15388/informatica.2003.001 fatcat:aopxcg56ujc2njch2fuovxdky4

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems

T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, M. Huebner, J. Becker, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Gerard Rauwerda, Daniel Menard, Olivier Sentieys (+7 others)
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
a Scilab-and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction.  ...  Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware -introduced by software parallelism of multiple cores and the flexibility of reconfigurable  ...  Beyond that, the ADL-based approach enables the ALMA toolset to support other target architectures. 4) It enables support for reconfigurable architectures since it allows to flexible target all configurations  ... 
doi:10.1109/recosoc.2012.6322879 dblp:conf/recosoc/StripfOBKHBRSKDMKMGAVDMSGP12 fatcat:ztmty66zq5d3hol7j5fenoxcxa

A Review on Embedded FPGAs Architectures and Configuration Tools

2019 Turkish Journal of Electrical Engineering and Computer Sciences  
In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance  ...  Embedded field programmable gate arrays (eFPGAs) represent a viable alternative to overcome these issues since they provide postmanufacturing flexibility that can reduce the number of chip redesigns and  ...  Acknowledgment This work is supported by Computer and Embedded Systems Laboratory and Digital Research Center of Sfax.  ... 
doi:10.3906/elk-1901-193 fatcat:kimby27rrbfyte4t2bh3lqtg3q

Soft IP Customisation Model Based on Metaprogramming Techniques

Vytautas Štuikys, Robertas Damaševičius
2004 Informatica  
We propose a layered Soft IP Customisation (SIPC) model for specifying and implementing system-level soft IP design processes such as wrapping and customisation.  ...  The SIPC model has three layers: (1) Specification Layer for specification of a customisation process using UML class diagrams, (2) Generalisation Layer for representation of a customisation process using  ...  Acknowledgements We thank the anonymous reviewers for their comments that allow us to improve the paper.  ... 
doi:10.15388/informatica.2004.049 fatcat:buzu3xgclfdrhkcz76nhx4qici

IEEE Standard 1500 Compliance Verification for Embedded Cores

A. Benso, S. Di Carlo, P. Prinetto, Y. Zorian
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Politano, A. Mouth, and L. Melchionda for their help in the development of this manuscript.  ...  In order to implement the syntax verification it is enough to implement a parser and a lexer for the CTL language.  ...  INTRODUCTION T HE INCREASED density and performance of advanced silicon technologies made system-on-a-chip (SoC) application-specific integrated circuits (ASICs) possible.  ... 
doi:10.1109/tvlsi.2008.917412 fatcat:kr2ly6guu5hind2v6d4usgfrpe

Design methodology for a modular service-driven network processor architecture

Maria Gabrani, Gero Dittmann, Andreas Döring, Andreas Herkersdorf, Patricia Sagmeister, Jan van Lunteren
2003 Computer Networks  
We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized  ...  Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network  ...  for their stimulating marketing insight and valuable customer validation support.  ... 
doi:10.1016/s1389-1286(02)00453-x fatcat:qiznjwsvqza57ez6xiehwtrlca

DrawerPipe: A Reconfigurable Pipeline for Network Processing on FPGA-Based SmartNIC

Junnan Li, Zhigang Sun, Jinli Yan, Xiangrui Yang, Yue Jiang, Wei Quan
2019 Electronics  
For most tenants with limited hardware design ability, it is time-consuming to develop NFs from scratch due to the lack of a rapidly reconfigurable framework.  ...  Finally, we implemented several highly reusable modules for low-level packet processing, and extended four example NFs (firewall, stateful firewall, load balancer, IDS) based on DrawerPipe.  ...  Acknowledgments: The authors would like to thank the anonymous reviewers for their valuable feedback. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics9010059 fatcat:mei5qxvl75ho5fo3w25ichfjgu

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldana, Paul Chow
2006 2006 International Conference on Field Programmable Logic and Applications  
and on-chip verification.  ...  This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols between processing elements  ...  Figure 4 shows a block diagram of the CE architecture for the MPEG-1 application based on Figure 1 's abstraction.  ... 
doi:10.1109/fpl.2006.311227 dblp:conf/fpl/ShannonFPPSC06 fatcat:gs7omnf5ffed5pguzwnlokvh4a

Application of design patterns for hardware design

Robertas Damaševičius, Giedrius Majauskas, Vytautas Štuikys
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We propose a Wrapper design pattern for adapting the behavior of the soft IPs, and demonstrate its application to the communication interface synthesis.  ...  We argue that hardware design patterns could be used for customizing and integrating the Intellectual Property (IP) components into Systemon-Chip designs.  ...  [16] propose a design methodology for SoC based on UML and C++/SystemC. UML is used as a modeling language extended for parallelism, structure, and timing.  ... 
doi:10.1145/775844.775847 fatcat:4egjlkuxibekvcgewn5qqy4pzq
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