878 Hits in 2.2 sec

QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks

Sunil Shukla, Neil W. Bergmann, Jurgen Becker
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
By applying the model at architectural level in QUKU, better hardware efficiency is achieved for a wide domain of applications.  ...  This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum architectural template for coarse grain array on per application basis.  ...  The fine grained structure of FPGAs has been seen as being unsuitable for implementing coarse grain algorithms.  ... 
doi:10.1109/ipdps.2007.370382 dblp:conf/ipps/ShuklaBB07 fatcat:yfebcq7hundhhe5b7uhssh6koe

Reconfigurable Computing for Space [chapter]

Donohoe, Gregory W., Lyke James
2010 Aerospace Technologies Advancements  
Interconnect structure The interconnect structure provides dedicated data paths within a configuration cycle.  ...  The challenge for dataflow architectures (and similar computational structures implemented in FPGAs), is to create "circuitizeable" code.  ...  Reconfigurable Computing for Space, Aerospace Technologies Advancements, Thawar T.  ... 
doi:10.5772/6939 fatcat:qiy3vly24ndm3eikjutrfzwceu

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei
2019 ACM Computing Surveys  
This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed.  ...  and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software.  ...  As a result, CGRAs are a superior alternative to FPGAs in accelerating applications. However, there is a lack of killer applications for CGRAs.  ... 
doi:10.1145/3357375 fatcat:pqi4d33i6bg45a6llswhwd44qi

Re-configurable computing in wireless

Bill Salefski, Levent Caglar
2001 Proceedings of the 38th conference on Design automation - DAC '01  
We outline how a designer works with the Chameleon reconfigurable processor from algorithm design to prototyping on a development module.  ...  Wireless communications requires a new approach to implement the algorithms for new standards.  ...  However, for increased bandwidth on the RCP, the designer can use the PIOs and structure the algorithm so it follows a streaming dataflow model.  ... 
doi:10.1145/378239.378459 dblp:conf/dac/SalefskiC01 fatcat:6o2nceramrb7xguo7cf6hrktpi

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Claudio Rubattu, Francesca Palumbo, Carlo Sau, Ruben Salvador, Jocelyn Serot, Karol Desnos, Luigi Raffo, Maxime Pelcat
2019 IEEE Embedded Systems Letters  
In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity  ...  Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems.  ...  CGR architectures are traditionally composed of a mesh of Processing Elements (PEs) whose interconnections are reconfigured over time [16] to offer flexibility.  ... 
doi:10.1109/les.2018.2882989 fatcat:uh7mhmyw4bh4xciykwb6bnepgy

A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios

Ganda Stephane Ouedraogo, Matthieu Gautier, Olivier Sentieys
2014 EURASIP Journal on Advances in Signal Processing  
This paper describes a novel design flow for FPGA-based SDR applications. This flow relies upon high-level synthesis (HLS) principles and leverages the nascent HLS tools.  ...  As this technology evolves, low-level designing methods for prototyping FPGA-based applications did not change throughout the decades.  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their comments and suggestions which helped improve this paper.  ... 
doi:10.1186/1687-6180-2014-164 fatcat:kc7tw2jfjjdrhk5ojnwjae4y7a

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
2020 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper.  ...  As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study.  ...  [91] proposed an FPGA-based flexible and efficient architecture suitable for different kinds of convolutional layers in DNNs.  ... 
doi:10.1109/jetcas.2020.3022920 fatcat:idqitgwnrnegbd4dhrly3xsxbi

Wires on Demand: Run-Time Communication Synthesis for Reconfigurable Computing

P. Athanas, J. Bowen, T. Dunham, C. Patterson, J. Rice, M. Shelburne, J. Suris, M. Bucciero, J. Graf
2007 2007 International Conference on Field Programmable Logic and Applications  
In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing a variety of datapaths.  ...  Our approach allocates a sandbox region in which modules from a library can be flexibly placed and interconnected.  ...  A wrapper structure supporting horizontal dataflow is shown in Figure 1 .  ... 
doi:10.1109/fpl.2007.4380705 dblp:conf/fpl/AthanasBDPRSSBG07 fatcat:qszz4xuwanb6xpzoxnq5rgui6a

An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture

Ricardo Ferreira, Julio Goldner Vendramini, Lucas Mucida, Monica Magalhaes Pereira, Luigi Carro
2011 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11  
Coarse-grained reconfigurable architecture has emerged as a promising model for embedded systems as a solution to reduce the complexity of FPGA synthesis and mapping steps, consequently reducing reconfiguration  ...  The proposed architecture consists of a set of heterogeneous functional units (FU) and a global interconnection network.  ...  Current FPGA devices provide flexibility by having a large number of fine-grained reconfigurable units and interconnection elements.  ... 
doi:10.1145/2038698.2038728 dblp:conf/cases/FerreiraVMPC11 fatcat:pxx5cfute5civgmr3rgeilrefa

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

Sébastien Pillement, Olivier Sentieys, Raphaël David
2008 EURASIP Journal on Embedded Systems  
DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low.  ...  Plaks Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints.  ...  FPGAs have been the reconfigurable computing mainstream for a couple of years and achieved flexibility by supporting gate-level reconfigurability; that is, they can be fully optimized for any application  ... 
doi:10.1155/2008/562326 fatcat:r6kxdj4rdffsjjh6qfpv7yae5q

StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox [chapter]

Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
2000 Lecture Notes in Computer Science  
Combining module generation with a high-level programming tool in C++ gives the programmer the convenience to explore the flexibility of FPGAs on the arithmetic level and write the algorithms in the same  ...  We apply the principles of object-oriented programming to the design of stream architectures for reconfigurable computing.  ...  Shand for maintaining PamDC. Thanks to L. Séméria for discussions on the draft of this paper. The second author thanks his advisor Prof. H. Klar for support of this research.  ... 
doi:10.1007/3-540-44614-1_64 fatcat:i4u2dqlckbfmpadi7leowymv7u

General-purpose systolic arrays

K.T. Johnson, A.R. Hurson, B. Shirazi
1993 Computer  
The almost instant wide acceptance of workstations and desktop computers indicates that [hey were quickly recognized as giving the best and most flexible performance for the dollar.  ...  Rcal-time applications that require intensive 110 and computation need not consume all the resources of a supercomputer.  ...  Splash, for example, is a linear reconfigurable array appropriate for bit-level applications. An FPGA chip can be configured for one medium-size systolic element or for several simple systolic cells.  ... 
doi:10.1109/2.241423 fatcat:5pbdb7wypbbqzk7riagtv5jsvq

Dynamically Reconfigurable Architectures for Digital Signal Processing Applications [chapter]

Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy
2002 IFIP Advances in Information and Communication Technology  
In this paper we will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one targeted on third generation networks.  ...  Principles, realisations and comparative results will be exposed for some classical applications, targeted on different architectures.  ...  This kind of solution could provide a great computation power/cost ratio, which combines the flexibility of a CPU / reconfigurable architecture couple with the efficiency of applications dedicated cores  ... 
doi:10.1007/978-0-387-35597-9_6 fatcat:4l54btj76zeifgmmzj3cyrjm3u

The Multi-Dataflow Composer Tool: an open-source tool suite for Optimized Coarse-Grain Reconfigurable Hardware Accelerators and Platform Design

Carlo Sau, Tiziana Fanni, Claudio Rubattu, Luigi Raffo, Francesca Palumbo
2020 Microprocessors and microsystems  
A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs  ...  This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their  ...  Luca Fanni, a former employ of the University of Sassari, for providing the initial MATLAB code used to derived the  ... 
doi:10.1016/j.micpro.2020.103326 fatcat:rtjvmftv5rbipc74yg2wq3vorm

Dynamically adaptable architecture for real-time video processing

Nicolas Ngan, Eva Dokladalova, Mohamed Akil, Francois Contou-Carrere
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
A simplified version with four nodes has been implemented on an FPGA for a video application to show the adaptation mechanism between a pipelined and parallel structure.  ...  In this paper, we present a new adaptable ringbased architecture for video processing applications.  ...  A simplified version with four nodes has been implemented on an FPGA for a video application to show the adaptation mechanism between a pipelined and parallel structure.  ... 
doi:10.1109/iscas.2010.5537617 dblp:conf/iscas/NganDAC10 fatcat:gwofeu6adraffik2gtloqbtdue
« Previous Showing results 1 — 15 out of 878 results