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Reconfigurable Processor for Binary Image Processing
2013
IEEE transactions on circuits and systems for video technology (Print)
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Binary image processing is a powerful tool in many image and video applications. A reconfigurable processor is presented for binary image processing in this paper. ...
The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2S180 field-programmable gate array. ...
detection, and image feature extraction. ...
doi:10.1109/tcsvt.2012.2223872
fatcat:szrryqj6nfhkbc2gzpqvxese2q
A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection
2013
2013 IEEE International Conference on Acoustics, Speech and Signal Processing
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The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction, ...
In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. ...
Consequently, a lowpower and high-performance HOG feature extraction processor is necessary to widen the range of applications. ...
doi:10.1109/icassp.2013.6638112
dblp:conf/icassp/TakagiMIKY13
fatcat:vd56qmxe3zapbk2nnl3qbclni4
Advanced processing for high-bandwidth sensor systems
2000
Imaging Spectrometry VI
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The project team is currently working on reconfigurable computing technology and advanced feature extraction techniques, with an emphasis on their application to image and RF signal processing. ...
This paper presents reconfigurable computing technology and advanced feature extraction algorithm work and their application to multi-and hyperspectral image processing. ...
Perkins et al 1 Traditional feature extraction algorithms often relay on a given geometry and set of observing conditions. ...
doi:10.1117/12.406575
fatcat:flyptmdyjvhozgeeejpw2rfhpm
Reconfigurable computing for future vision-capable devices
2015
2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
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architectures: A low-power EnCore processor with a Configurable Flow Accelerator co-processor, a hybrid reconfigurable SIMD/MIMD platform and Transport-Triggered Architecture-based processors. ...
In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant ...
The first one is capable of performing LBP feature extraction for HDTV resolution video at a modest clock frequency of 304MHz in real time [20] [25] . ...
doi:10.1109/samos.2015.7363657
dblp:conf/samos/LopezNSBV15
fatcat:ljzx4e4iv5a6jidj2abdwcefo4
Exploiting run-time reconfigurable hardware in the development of automatic fingerprint-based personal recognition applications
[chapter]
2011
Recent Application in Biometrics
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The key objective of the book is to provide a collection of comprehensive references on some recent theoretical development as well as novel applications in biometrics. ...
doi:10.5772/21500
fatcat:bxmridfkd5bkfif3ffnfmmnazi
Neuromorphic vision chips
2018
Science China Information Sciences
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The FD neuromorphic reconfigurable vision chip comprises a high speed image sensor, a processing element array and self-organizing map neural network. ...
in the three dimensional (3D) large-scale integrated circuit (LSI) technology becomes a trend of the research on the vision chip. ...
Secondly, the chips only implement a single-kernel convolution and feature extraction. ...
doi:10.1007/s11432-017-9303-0
fatcat:tnl2guf3yvczhgdlmkclhvgsqy
Special issue on real time biometrics and secure media
2013
Journal of Real-Time Image Processing
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Laadjel et al. present a bimodal biometric recognition system based on the extracted features of the human palmprint and iris. ...
The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dualcore processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical ...
In the proposed approach, the extracted key points are mapped to processors on a hypercube architecture with a shared global memory structure. ...
doi:10.1007/s11554-013-0369-7
fatcat:6lsfp6jh7nd6tohdlp4gbzkfhe
A High-Speed Vision System for Moment-Based Analysis of Numerous Objects
2007
2007 IEEE International Conference on Image Processing
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The proposed system achieves high-speed image processing by providing a dedicated massively parallel co-processor for moment extraction. ...
The co-processor has a high-performance core based on a pixel-parallel and object-parallel calculation method. We constructed a prototype system and evaluated its performance. ...
Depending on the application, a recognition process using the extracted features may be added to the CPU. ...
doi:10.1109/icip.2007.4379794
dblp:conf/icip/WatanabeKI07
fatcat:tisv52dflfaphb6o2oseiuiatu
A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
2013
IEICE transactions on electronics
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This paper describes a Histogram of Oriented Gradients (HOG) feature extraction accelerator that features a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification ...
The dual core architecture enables parallel feature extraction in one frame for high-speed or low-power computing and detection of multiple objects simultaneously with low power consumption by HOG feature ...
Consequently, a low-power and high-performance HOG feature extraction processor is necessary to widen the range of applications. ...
doi:10.1587/transele.e96.c.433
fatcat:nfa7mjmbencyneonhgfexynu3y
RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS
2017
Asian Journal of Pharmaceutical and Clinical Research
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Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for ...
This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality ...
Thus, FPGA becomes a trade-off to application specific integrated circuit with reconfigurable feature [2] . ...
doi:10.22159/ajpcr.2017.v10s1.19632
fatcat:uu2crmcltvgdtparrdzwszig7u
Reconfigurable On-Board Vision Processing for Small Autonomous Vehicles
2007
EURASIP Journal on Embedded Systems
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We describe a custom FPGA-based circuit board designed to support research in the development of algorithms for image-directed navigation and control. ...
This paper addresses the challenge of supporting real-time vision processing on-board small autonomous vehicles. ...
In fact, some of the classic reconfigurable computing papers demonstrated image processing applications on FPGA-based systems (e.g., see [11] ). ...
doi:10.1186/1687-3963-2007-080141
fatcat:yzkolrcztfgrfb2jl44u7bjxi4
Reconfigurable On-Board Vision Processing for Small Autonomous Vehicles
2007
EURASIP Journal on Embedded Systems
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We describe a custom FPGA-based circuit board designed to support research in the development of algorithms for image-directed navigation and control. ...
This paper addresses the challenge of supporting real-time vision processing on-board small autonomous vehicles. ...
In fact, some of the classic reconfigurable computing papers demonstrated image processing applications on FPGA-based systems (e.g., see [11] ). ...
doi:10.1155/2007/80141
fatcat:sqk74x4rsjfijhekmfalimxflm
Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware
2010
IEEE Transactions on Circuits and Systems - II - Express Briefs
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system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance ...
To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable ...
This feature is known as dynamic partial self-reconfiguration. ...
doi:10.1109/tcsii.2010.2087970
fatcat:ono2r6syerdzzggfnnsmbw3z6e
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams
2013
IEEE Journal of Solid-State Circuits
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multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. ...
A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. ...
It contains of 4 simultaneous multithreading feature extraction cluster (SFEC) for SIFT feature extraction operation, a feature
Fig. 4 . 4 (a) 5-stage fine-grain pipeline stages and (b) its pipeline ...
doi:10.1109/jssc.2012.2220651
fatcat:uh4ec3i64vdmjdev5sgck7iv2i
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation
2020
IEEE Access
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This paper describes a reconfigurable architecture for an on-board processor to be used in space exploration critical systems. ...
.: Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation ...
The absolute navigation technique relies on surface features detection and matching of a priori extracted landmarks. ...
doi:10.1109/access.2020.2983308
fatcat:j72ts3hlencxbcfe74cw23bjrm
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