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Big Data Analytics Architecture and Challenges, Issues of Big Data Analytics

S. Senthil Kumar, Ms.V. Kirthika
2017 International Journal of Trend in Scientific Research and Development  
Big Data technologies uses a new generation of technologies and architectures, designed for organizations can extract value from very large volumes of a wide variety of data by enabling high velocity capture  ...  Big data is a massive amount of digital data being collected from various sources that are too large. Big data deals with challenges like complexity, security, risks to privacy.  ...  However, Twister has fault-tolerant issues due to in memory processing.  ... 
doi:10.31142/ijtsrd4673 fatcat:e4cw7hr67rbndmfflppgkarz4a

Massively Parallel Processor Architectures for Resource-aware Computing [article]

Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
2014 arXiv   pre-print
Finally, we will introduce ideas on how to realize fault-tolerant loop execution on such massively parallel architectures through employing on-demand spatial redundancies at the processor array level.  ...  We present a class of massively parallel processor architectures called invasive tightly coupled processor arrays (TCPAs).  ...  As a remedy, we present a domain-specific class of massively parallel processor architectures called invasive tightly coupled processor arrays (TCPA), which offer built-in and scalable resource management  ... 
arXiv:1405.2907v1 fatcat:uardefsilngdnbllkg5qkmsxha

From massively parallel image processors to fault-tolerant nanocomputers

J. Han, P. Jonker
2004 Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004.  
for a massively parallel architecture based on molecular or nanoelectronic devices.  ...  In this paper, we present a fault-tolerant technique suitable for an implementation in nanoelectronics, the triplicated interwoven redundancy (TIR).  ...  An NIR implementation of a PE structure, as the one studied in our paper, can be used as the building blocks of a massively parallel, yet fault-tolerant computer architecture.  ... 
doi:10.1109/icpr.2004.1334455 dblp:conf/icpr/HanJ04 fatcat:oys235bhofdaxnc7ke2xhlpgqq

Author index

2006 2006 IEEE International Conference on Cluster Computing  
Superscheduling Scheme for Computational Grids Henderson, Keith MSSG: A Framework for Massive-Scale Semantic Graphs Herault, Thomas FAIL-MPI: How Fault-Tolerant Is Fault-Tolerant MPI?  ...  : How Fault-Tolerant Is Fault-Tolerant MPI?  ... 
doi:10.1109/clustr.2006.311921 fatcat:vmbbimypuze7ncjqfonu4po5l4

Biologically Inspired Robust Tera-Device Processors

Michael Nicolaidis
2012 IEEE Design & Test of Computers  
Thus, single-chip, massively parallel architectures will be made possible through the dense integration of a huge number of devices.  ...  The above two factors call for a self-healing, massively parallel computing paradigm as a key enabler for exploiting future technologies to implement single-chip, massively parallel computers comprising  ... 
doi:10.1109/mdt.2012.2211174 fatcat:rfl2pmrkrbgpbgetykpgz5brxi

Supervised Workpools for Reliable Massively Parallel Computing [chapter]

Robert Stewart, Phil Trinder, Patrick Maier
2013 Lecture Notes in Computer Science  
This paper presents a software level reliability mechanism, namely supervised fault tolerant workpools implemented in a Haskell DSL for parallel programming on distributed memory architectures.  ...  Therefore, massively parallel compute jobs must be able to tolerate failures. For example, in the HPC-GAP project we aim to coordinate symbolic computations in architectures with 10 6 cores.  ...  They provide high level abstractions for fault tolerant parallel computation on distributed-memory architectures. To the best of our knowledge the supervised workpool is a novel construct.  ... 
doi:10.1007/978-3-642-40447-4_16 fatcat:5j5e2ciccndhjo6lsogekogbxe

RIDE: real-time massive image processing platform on distributed environment

Yoon-Ki Kim, Yongsung Kim, Chang-Sung Jeong
2018 EURASIP Journal on Image and Video Processing  
Finally, it supports dynamic fault tolerance for real-time image processing through the coordination between components in our system.  ...  It minimizes communication overhead by using a parallel processing strategy which handles the stream data considering both coarse-grained and fine-grained parallelism simultaneously.  ...  Each stage in an application topology is a unit of processing the task, and the whole application topology has a great advantage for higher performance, Fault tolerance RIDE supports dynamic fault tolerance  ... 
doi:10.1186/s13640-018-0279-5 fatcat:lw2wxcnxcradpkphwv2njy7v7a

Architectures for silicon nanoelectronics and beyond

R.I. Bahar, C. Lau, D. Hammerstrom, D. Marculescu, J. Harlow, A. Orailoglu, W.H. Joyner, M. Pedram
2007 Computer  
And any paradigm shift in applications and architecture will have a profound effect on the design process and tools required.  ...  We can't develop an architecture without a sense  ...  and Microtechnologies Institute (ONAMI), "Architectures for Silicon Nanoelectronics and Beyond: A Workshop to Chart Research Directions," workshop/index.htm.  ... 
doi:10.1109/mc.2007.7 fatcat:gp72twusgjdn5b5kh6sehsnpqm

Deploying fault tolerance and taks migration with NetSolve

James S. Plank, Henri Casanova, Micah Beck, Jack J. Dongarra
1999 Future generations computer systems  
A fundamental feature of NetSolve is its integration of fault-tolerance and task migration in a way that is transparent to the end user.  ...  Computational power grids are computing environments with massive resources for processing and storage.  ...  There has been a vast amount of research on embedding fault-tolerance and load-balancing into parallel and distributed computing platforms.  ... 
doi:10.1016/s0167-739x(99)00024-2 fatcat:hciy7gcjdvgihnxdcokno6i6yi

Deploying fault-tolerance and task migration with NetSolve [chapter]

James S. Plank, Henri Casanova, Micah Beck, Jack Dongarra
1998 Lecture Notes in Computer Science  
Computational power grids are computing environments with massive resources for processing and storage.  ...  A fundamental feature of NetSolve is its integration of fault-tolerance and task migration in a way that is transparent t o the end user.  ...  Checkpointing in CosMiC: a user-level process migration environment. In Paci c Rim International Symposium on Fault-Tolerant Systems, December 1997.  ... 
doi:10.1007/bfb0095364 fatcat:l32o2opv5neqlcrpxqp55mnqwm

The impact of the soft errors in convolutional neural network on GPUs: Alexnet as case study

Khalid Adam, Izzeldin I. Mohd, Younis M. Younis
2021 Procedia Computer Science  
., fault injector). Results show that FADD and LD are the top vulnerable instructions against soft errors for Alexnet model, both instructions generate at least 84% of injected faults as SDC errors.  ...  In this paper, we experimentally evaluate the vulnerable parts of Alexnet mode (e.g., fault injector).  ...  CNNs have high massive parallelism structure and require high computational capabilities such as Graphics Processing Units (GPUs).  ... 
doi:10.1016/j.procs.2021.02.012 fatcat:jwloam4rcbhbpncybbdmwwszzi

Parallel Processing of cluster by Map Reduce

Madhavi Vaidya
2012 International Journal of Distributed and Parallel systems  
Massive input, spread across many machines, need to parallelize. Moves the data, and provides scheduling, fault tolerance.  ...  Map Reduce has gained a great popularity as it gracefully and automatically achieves fault tolerance.  ...  MapReduce is a widely used method of parallel computation on massive data.  ... 
doi:10.5121/ijdps.2012.3113 fatcat:77eseounhzdqjmknjh4yleg2dy

Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation

Shuo Wang, Lei Wang, Faquir Jain
2009 ACM Journal on Emerging Technologies in Computing Systems  
By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance.  ...  The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing.  ...  ., error correcting codes, are effective to deal with faults in interconnect and memory. To exploit parallel processing, pipelined architecture is implemented in the clusters.  ... 
doi:10.1145/1482613.1482615 fatcat:ipoydlx7mnb5fjz22dmd4rbmc4

Page 350 of IEEE Transactions on Computers Vol. 52, Issue 3 [page]

2003 IEEE Transactions on Computers  
His research interest include real-time and fault-tolerant systems, optical interconnection networks, high performance computing, and parallel computer architectures.  ...  Dr Melhem served on program committees of numerous conferences and workshops and was the general chair for the Third Internationa Conference on Massively Parallel Processing Using Optical Intercon- nections  ... 

A defect- and fault-tolerant architecture for nanocomputers

Jie Han, Pieter Jonker
2003 Nanotechnology  
In this paper, we review these two techniques, and present a defect-and fault-tolerant architecture in which von Neumann's NAND multiplexing is combined with a massively reconfigurable architecture.  ...  Both von Neumann's NAND multiplexing, based on a massive duplication of imperfect devices and randomized imperfect interconnects, and reconfigurable architectures have been investigated to come up with  ...  µ= 1 µ = 2 µ = 5 µ = 20 µ = ∞ In summary, we have discussed a set-up of a massively parallel fault-tolerant computer architecture.  ... 
doi:10.1088/0957-4484/14/2/324 fatcat:t7whyj6l5rboxkw37dx22m4gby
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