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A Faster-than Relation for Asynchronous Processes [chapter]

Gerald Lüttgen, Walter Vogler
2001 Lecture Notes in Computer Science  
This paper introduces a novel (bi)simulation{based faster{than preorder which relates asynchronous processes with respect to their worst{case timing behavior.  ...  This paper introduces a novel bisimulation based faster than preorder which relates asynchronous processes with respect to their worst case timing behavior.  ...  This justi es our faster than preorder as a reference preorder for relating asynchronous processes with respect to their worst case timing behavior.  ... 
doi:10.1007/3-540-44685-0_18 fatcat:opcdogzlgbegzctvvsl6ppmg5m

Modeling and Implementation of an Asynchronous Approach to Integrating HPC and Big Data Analysis 1

Yuankun Fu, Fengguang Song, Luoding Zhu
2016 Procedia Computer Science  
The experiments show that the analytic model exhibits an average relative error of less than 10%, and the application performance can be improved by up to 131% for the synthetic programs and by up to 78%  ...  for the real-world CFD application.  ...  Both the fully asynchronous pipeline method and the improved traditional method are faster than the traditional method. For instance, they are 31% faster with the block size of 8MB.  ... 
doi:10.1016/j.procs.2016.05.297 fatcat:fmbsrcvzl5eczemskzvhxhuhwm

Page 428 of The Journal of Neuroscience Vol. 24, Issue 2 [page]

2004 The Journal of Neuroscience  
Our results are compatible with these assumptions be- cause the time constant expected for an asynchronous release rate of 2.8 RRPs/sec (1/2.8 = 360 msec) is faster than the RRP recov- ery (T,), based  ...  The RRP is refilled by either a slow process (‘T, (moder) from R, or fast process (‘T's (moger)) from R;.  ... 

VeloC: Towards High Performance Adaptive Asynchronous Checkpointing at Large Scale

Bogdan Nicolae, Adam Moody, Elsa Gonsiorowski, Kathryn Mohror, Franck Cappello
2019 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS)  
This problem is not well understood but highly important for modern supercomputing infrastructures. This paper proposes a versatile asynchronous checkpointing solution that addresses this problem.  ...  To address this issue, a shift from synchronous checkpointing (i.e., blocking until writes have finished) to asynchronous checkpointing (i.e., writing to faster local storage and flushing to external storage  ...  Nuclear Security Administration, responsible for the planning and preparation of a capable exascale ecosystem, including software, applications, hardware, advanced system engineering and early testbed  ... 
doi:10.1109/ipdps.2019.00099 dblp:conf/ipps/NicolaeMGMC19 fatcat:6anbo4rezvedleejttnowfmnpe

Accelerating Asynchronous Stochastic Gradient Descent for Neural Machine Translation [article]

Nikolay Bogoychev, Marcin Junczys-Dowmunt, Kenneth Heafield, Alham Fikri Aji
2018 arXiv   pre-print
We introduce local optimizers which mitigate the stale gradient problem and together with fine tuning our momentum we are able to train a shallow machine translation system 27% faster than an optimized  ...  In order to achieve further speedup we introduce a technique that delays gradient updates effectively increasing the mini-batch size.  ...  Acknowledgments We thank Adam Lopez, Sameer Bansal and Naomi Saphra for their help and comments on the paper. We thank our reviewers for their comments and suggestions.  ... 
arXiv:1808.08859v2 fatcat:6hopnc2tlzhgnf2pnevvletnme

Accelerating Asynchronous Stochastic Gradient Descent for Neural Machine Translation

Nikolay Bogoychev, Kenneth Heafield, Alham Fikri Aji, Marcin Junczys-Dowmunt
2018 Proceedings of the 2018 Conference on Empirical Methods in Natural Language Processing  
We introduce local optimizers which mitigate the stale gradient problem and together with fine tuning our momentum we are able to train a shallow machine translation system 27% faster than an optimized  ...  In order to achieve further speedup we introduce a technique that delays gradient updates effectively increasing the mini-batch size.  ...  Acknowledgments We thank Adam Lopez, Sameer Bansal and Naomi Saphra for their help and comments on the paper. We thank our reviewers for their comments and suggestions.  ... 
doi:10.18653/v1/d18-1332 dblp:conf/emnlp/BogoychevHAJ18 fatcat:wtnk5yjkwfabnhhccsl62fy6ju

FPGA based Asynchronous FIR Filter Design for ECG Signal Processing

Rahul Sharma, Rajesh Mehra, Chandni C.
2016 International Journal of Computer Applications  
In this paper, Asynchronous FIR filter is designed and implemented for ECG signal processing.  ...  The hardware result shows that the proposed asynchronous designed on Virtex 2P is 10.72% faster than that designed on synchronous FIR filter on given specifications.  ...  This shows Asynchronous design is 10.72% faster than synchronous design in Virtex 2P and 10.01% faster in Spartan-3E.  ... 
doi:10.5120/ijca2016912463 fatcat:v5djkhjdyjhzrlsz2wamvxaeza

Distributed deep learning platform for pedestrian detection on IT convergence environment

Seong-Soo Han, Yoon-Ki Kim, You-Boo Jeon, JinSoo Park, Doo-Soon Park, DuHyun Hwang, Chang-Sung Jeong
2020 Journal of Supercomputing  
However, since deep learning for pedestrian detection is timeconsuming for processing a large volume of image data, it requires a lot of computing resources, and hence building such a system is very expensive  ...  Our platform provides a convenient interface for easily and efficiently executing the deep learning process in a distributed environment by providing a multilayered system architecture.  ...  To view a copy of this licence, visit http://creat iveco mmons .org/licen ses/by/4.0/.  ... 
doi:10.1007/s11227-020-03195-0 fatcat:2lotrkavwjcszhsr2jnzoi3nia

Faster asynchronous systems

Walter Vogler
2003 Information and Computation  
The resulting testing-preorder is characterized with a variant of refusal traces and shown to satisfy some properties that make it attractive as a faster-than relation.  ...  Finally, one implementation of a bounded buffer is shown to be strictly faster than two others -in contrast to a result obtained with a different approach by Arun-Kumar and Hennessy.  ...  Nevertheless, we will develop a scenario of must-testing with time bounds for asynchronous systems and base a useful faster-than relation on it.  ... 
doi:10.1016/s0890-5401(03)00065-8 fatcat:epjosjmdjrfrzonebhucrvvnxa

Effect of harmonic relatedness on the detection of temporal asynchronies

Barbara Tillmann, Jamshed J. Bharucha
2002 Perception & Psychophysics  
This research has been supported in part by a grant to B.T. from the Deutsche Akademische Austauschdienst DAAD and by grants to J.J.B. from the National Science Foundation (SBR-9601287) and NIH (2P50  ...  Results showed that harmonic relatedness influences the processing of the target chord: Phoneme monitoring was faster for phonemes sung on a strongly related target (a referential tonic chord) than for  ...  Overall, response times were faster for synchronous targets than for asynchronous targets [F(1,14) = 17.5, MS e = 2,455.34, p < .01].  ... 
doi:10.3758/bf03194732 pmid:12132764 fatcat:5o6syi4j2ncczfsmme2bkhpbwa

Iterative Sparse Triangular Solves for Preconditioning [chapter]

Hartwig Anzt, Edmond Chow, Jack Dongarra
2015 Lecture Notes in Computer Science  
We also illustrate the effect of using asynchronous iterations.  ...  We demonstrate the performance gains that this approach can have on GPUs in the context of solving sparse linear systems with a preconditioned Krylov subspace method.  ...  The results show that the block-asynchronous methods converge faster than the classical Jacobi methods.  ... 
doi:10.1007/978-3-662-48096-0_50 fatcat:k4p5ysqnhza3djruia4kvsc5j4

Experimental Analysis of Rumor Spreading in Social Networks [chapter]

Benjamin Doerr, Mahmoud Fouz, Tobias Friedrich
2012 Lecture Notes in Computer Science  
For the asynchronous version of the rumor spreading protocol, we observe that the theoretically predicted asymptotic advantage of preferential attachment graphs is smaller than expected.  ...  Aside from extremely sparse graphs, preferential attachment graphs perform faster than all other graph classes examined.  ...  faster than in complete graphs ( ) for m = 10.  ... 
doi:10.1007/978-3-642-34862-4_12 fatcat:qlozimt5srdr5m7on4adeactpa

Asynchronous Methods for Model-Based Reinforcement Learning [article]

Yunzhi Zhang, Ignasi Clavera, Boren Tsai, Pieter Abbeel
2019 arXiv   pre-print
We evaluate our asynchronous framework on a range of standard MuJoCo benchmarks. We also evaluate our asynchronous framework on three real-world robotic manipulation tasks.  ...  In this work, we propose an asynchronous framework for model-based reinforcement learning methods that brings down the run time of these algorithms to be just the data collection time.  ...  Our empirical investigation shows that asynchronous model-based RL learns substantially faster than prior approaches.  ... 
arXiv:1910.12453v1 fatcat:elu5qvs4pjddhoplcvkgomgjty

Is it time for clockless chips? [Asynchronous processor chips]

D. Geer
2005 Computer  
Domino logic is also efficient because it acts only on data that has changed during processing, rather than acting on all data throughout the process.  ...  Rather than waiting for a clock tick, clockless-chip elements hand off the results of their work as soon as they are finished.  ...  To buy a reprint, send a query to computer@computer.org.  ... 
doi:10.1109/mc.2005.106 fatcat:fsjey4hk55avzcilfpxds6bcvi

How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design

G. Paci, A. Nackaerts, F. Catthoor, L. Benini, P. Marchal
2008 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools  
Rather than pursuing a worst-case design approach for dealing with these uncertainties, we present a hybrid selftimed/synchronous approach.  ...  Unfortunately, when operating near the threshold voltage, transistors become highly sensitive to process variations, thereby increasing leakage currents and complicating timing closure.  ...  For instance, a better-than-worst-case DLX processor designed in asynchronous logic using matched delaylines is presented [12] .  ... 
doi:10.1109/dsd.2008.114 dblp:conf/dsd/PaciNCBM08 fatcat:pl5bnopk65fztn5crwv4axtwx4
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