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Itanium processor microarchitecture
2000
IEEE Micro
Preserved Fulltext
EPIC hardware The Itanium processor introduces a number of unique microarchitectural features to support the EPIC design style. 2 These features focus on the following areas: • supplying plentiful fast ...
The Itanium processor is the first implementation of the IA-64 instruction set architecture (ISA). ...
doi:10.1109/40.877948
fatcat:22nth6t6lzhcza2v2xxj4wfcem
Fast Modular Reduction
2007
Computer Arithmetic
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It is widely acknowledged that efficient modular multiplication is a key to high-performance implementation of public-key cryptography, be it classical RSA, Diffie-Hellman, or (hyper-) elliptic curve algorithms ...
In this paper, we propose a modification to Barrett's algorithm that leads to a significant reduction (25% to 75%) in multiplications and additions. 18th IEEE Symposium on Computer Arithmetic(ARITH'07) ...
Finally, we consider Intel's 64-bit Itanium 2 processor, which can issue either six adds per cycle or four adds and two 64-bit integer multiplies per cycle. ...
doi:10.1109/arith.2007.18
dblp:conf/arith/HasenplaughGG07
fatcat:2imdvjregzdxdnlekqbfzemnjy
Xen and the art of virtualization
2003
Proceedings of the nineteenth ACM symposium on Operating systems principles - SOSP '03
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. • Guest OS may install a "fast" exception handler for system calls, allowing direct calls from an application into its guest OS and avoiding indirecting through Xen on every call. ...
• Xen is a virtual machine monitor (VMM) for x86, x86-64, Itanium and PowerPC architectures. ...
-Yes I think so, with 2 privilege levels Guest OS wouldn't be able to protect itself from applications. • If Xen VMM is not used on a processor X86 with four privilege levels, will the whole architecture ...
doi:10.1145/945445.945462
dblp:conf/sosp/BarhamDFHHHN03
fatcat:rbqmyunpkrc33daifth2xrycoy
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
2016
Journal of Cryptographic Engineering
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We classify types of attacks according to a taxonomy of the shared resources leveraged for such attacks. Moreover, we take a detailed look at attacks used against shared caches. ...
Sun/Oracle's T1 and later) or on a high-latency event (an L3 cache miss on Intel's Montecito Itanium); later Itanium processors switched from TMT to SMT. ...
from squarings in OpenSSL's RSA implementation. ...
doi:10.1007/s13389-016-0141-6
fatcat:7fvkr7h54rbl5mx6vrochsgtkm
Evaluation of four encryption algorithms for viability, reliability and performance estimation
2017
Nigerian Journal of Technological Development
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It enables one to store sensitive information or transmit it across computer in a more secured ways so that it cannot be read by anyone except the intended receiver. ...
Cryptography also allows secure storage of sensitive data on any computer. ...
For both uni-processor (local) as well as cloud (Appengine) environment, RSA is the most time consuming and MD5 is the least. ...
doi:10.4314/njtd.v13i2.5
fatcat:zs3n6vm7cffxfnqulxyxm4bkna
Intel SGX Explained
[article]
2016
IACR Cryptology ePrint Archive
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Intel's Software Guard Extensions (SGX) is a set of extensions to the Intel architecture that aims to provide integrity and confidentiality guarantees to securitysensitive computation performed on a computer ...
on SGX, a series of intelligent guesses about some important but undocumented aspects of SGX, and an analysis of SGX's security properties. ...
The core's execution units handle common cases in fast paths implemented in hardware. ...
dblp:journals/iacr/CostanD16
fatcat:vzg7uthif5fqfbx5pdz3ocs7va
High-performance computing systems: Status and outlook
2012
Acta Numerica
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, which has been one of their most remarkable characteristics. ...
This article describes the current state of the art of high-performance computing systems, and attempts to shed light on near-future developments that might prolong the steady growth in speed of such systems ...
The newest Itanium processor no longer plays a role in the HPC scene and is therefore also omitted. ...
doi:10.1017/s0962492912000050
fatcat:n6yodkox5zb6xmlep6gvayud2m
Selecting the advanced encryption standard
2003
IEEE Security and Privacy
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NIST considered a wealth of data regarding the candidates' performance on many platforms, including Pentiums, Itaniums, RISC processors, 8-bit embedded microprocessors, digital signal processors (DSPs) ...
Submitted by RSA Data Systems, RC6 is a simple, elegant algorithm that relies on multiplication and datadependent rotations but does not have S-boxes. ...
doi:10.1109/msecp.2003.1193210
fatcat:fusg7lp4lbetng3zrtglgajugq
VLSI implementations of threshold logic- a comprehensive survey
2003
IEEE Transactions on Neural Networks
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At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies. ...
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. ...
One is called pseudodynamic and "was highly leveraged across the Itanium 2 processor" [35] , [36] . ...
doi:10.1109/tnn.2003.816365
pmid:18244573
fatcat:o3ch3ze3xre5pewnvo7d4lh2uu
Embedded System Hardware
[chapter]
2021
Embedded Systems
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The need to cover other hardware components as well is a consequence of their impact on the performance, timing characteristics, power consumption, safety, and security. ...
Efforts for making EPIC instruction sets available in the PC sector resulted in Intel's IA-64 instruction set [249] and its implementation in the Itanium ® processor. ...
Soft cores can be implemented on any FPGA chip. ...
doi:10.1007/978-3-030-60910-8_3
fatcat:fqsp2laanfhp5le2d5q3pft2cu
Hints and Principles for Computer System Design
[article]
2021
arXiv
pre-print
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So does a multiprocessor that implements total store order: all the processors share the RAM, and each processor has a private write buffer holding its writes that have not yet made it to RAM. ...
Then 2 satisfies 1 is just 2 ⇒ 1 : every behavior that satisfies 2 also satisfies 1 . So implementation is implication. This story works for any system. ...
arXiv:2011.02455v3
fatcat:jolyz5lknjdbpjpxjcrx5rh6fa
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs
2014
2014 International Test Conference
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The main feature of these tools is that they implement a model of SEUs affecting the configuration bits controlling the logic and routing resources of an FPGA device that has been demonstrated to be much ...
they can also permanently change the functionality implemented by the system itself, by changing the content of the configuration memory. ...
FPGA APPLICATION FIELDS Examples of processor prototyping using FPGA devices are: [192] where a Xilinx Virtex II is used to implement a fully programmable prototype of an Intel Itanium processor; [92 ...
doi:10.1109/test.2014.7035366
dblp:conf/itc/Cassano14
fatcat:ykg7k6finnhwpk7j6zsbtlwfkq
A new binary arithmetic for finite-word-length linear controllers: MEMS applications
2014
2014 9th International Design and Test Symposium (IDT)
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of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation. ...
The radix-2 r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with a Kalman filter. ...
While radix-16 is used only in the most recent Intel processors: 64 and IA-32 [13] , and Itanium-Poulson [14] . ...
doi:10.1109/idt.2014.7038608
dblp:conf/idt/OudjidaLBC14
fatcat:ykr7hhrd7ndy5jbmu53hb3t7vm
Platform Independence 2010 - Helping Documents Fly Well in Emerging Architectures
Proceedings of Balisage: The Markup Conference 2010
unpublished
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Conventional wisdom is now to double the number of cores on a chip with each silicon generation. ...
The recent switch to parallel microprocessors is a milestone in the history of computing. ...
Berkeley, on sabbatical from MIT. ...
doi:10.4242/balisagevol5.wrightson01
fatcat:sqpbc7yeefcnnhc3m7tw5afhrm
Light-Weight, Runtime Verification of Query Sources
2009
Proceedings / International Conference on Data Engineering
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It is lightweight in three ways: (1) We use the Merkle hash tree data structure and fast cryptographic hash functions to ensure the verification itself is fast and secure; (2) We verify the minimum number ...
Finally, we perform a comprehensive empirical study on various parameter choices and on the system performance and concurrency with our approaches. Hash tag of a sub-block ...
The processor can finish one hash operation in one hash step. ...
doi:10.1109/icde.2009.40
dblp:conf/icde/GeZ09
fatcat:rb5jkumkybfqpjq3id7dsmisva
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