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Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications

Wei-chun Ku, Shu-hsuan Chou, Jui-chin Chu, Chih-heng Kang, Tien-fu Chen, Jiun-in Guo
2006 2006 IEEE International Conference on Multimedia and Expo  
In this paper, a UniCore VisoMT processor is proposed, which unifies VLIW and multithreading by providing an efficient control and data communication model, while offering explicit parallelisms for embedded  ...  The architecture concurrently executes a main thread and several accelerative threads, coordinated by the main thread.  ...  UniCore VisoMT Processor Architecture The UniCore VisoMT model unifies VLIW with simultaneously multithreading to achieve high performance.  ... 
doi:10.1109/icme.2006.262505 dblp:conf/icmcs/KuCCKCG06 fatcat:bsuqbiln5rcxzpl5pto7bfo5im

Multithreaded Processors

T. Ungerer
2002 Computer journal  
The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor  ...  Dual path branch execution models A number of research projects survey eager execution-dual path execution of branches. They extend either superscalar or SMT processors.  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor  ...  Dual path branch execution models A number of research projects survey eager execution-dual path execution of branches. They extend either superscalar or SMT processors.  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

Multiprocessor simulation using communicating sequential processes

Pranav S. Vaidya, Jaehwan John Lee
2010 International Journal of Computer Aided Engineering and Technology  
Modeling and simulation are extremely important tools used for accurate performance prediction of multicore/multiprocessor systems.  ...  Furthermore, we show how this formal description of a multiprocessor system can be mapped to the primitives provided by the Kent C++CSP multithreading library to create a multithreaded multiprocessor simulator  ...  However, WWT II does not allow changes in the processor models and other architectural parameters such as issue widths, speculative memory accesses and out-of-order execution [23] .  ... 
doi:10.1504/ijcaet.2010.029599 fatcat:5wcz3aynzzdtjibtw5blxtxod4

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors

Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro Lopez
2007 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)  
In this paper, we present the Multi2Sim simulation framework, which models the major components of incoming systems, and is intended to cover the limitations of existing simulators.  ...  Current microprocessors are based in complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks.  ...  Acknowledgements This work was supported by CICYT under Grant TIN2006-15516-C04-01, by Consolider-Ingenio 2010 under Grant CSD2006-00046 and by the Generalitat Valenciana under grant GV06/326.  ... 
doi:10.1109/sbac-pad.2007.17 fatcat:litbjuzotnh2bo3s5hjgjbtoce

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor. and single-chip, multiple-issue multiprocessing  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/285930.286011 dblp:conf/isca/TullsenEL98a fatcat:wzwmqqcnj5bz3faupjps7d6tay

Execution and Cache Performance of the Scheduled Dataflow Architecture

Joseph Arul, Krishna Kavi, Roberto Giorgi
2000 Journal of universal computer science (Online)  
The analytical analysis of our architecture showed that we could achieve a better performance than other classical dataflow architectures (i.e., ETS), hybrid models (e.g., EARTH) and decoupled multithreaded  ...  A program is partitioned into functional execution threads, which are perfectly suited for our non-blocking multithreaded architecture.  ...  It is necessary to find an appropriate multithreaded model and implementation to achieve the best possible performance.  ... 
doi:10.3217/jucs-006-10-0948 dblp:journals/jucs/KaviAG00 fatcat:ayzfhn4jyra4jbhra6jpulqz6m

Maximizing CMP throughput with mediocre cores

J.D. Davis, J. Laudon, K. Olukotun
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
We use area models based on SPARC processors incorporating these architectural features.  ...  We examine CMTs with inorder scalar processor cores, 2-way or 4-way in-order superscalar cores, private primary instruction and data caches, and a shared secondary cache.  ...  Acknowledgements We would like to thank Cong Fu, Venkatesh Iyengar, and the entire Niagara Architecture Group for their assistance with the performance modeling.  ... 
doi:10.1109/pact.2005.42 dblp:conf/IEEEpact/DavisLO05 fatcat:h5rgzutzjndzhdtyndkrewxxhm

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
This research was supported by NSF grants MIP-9632977, CCR-9200832, and CCR-9632769, NSF PYI Award MIP-9058439, DEC Western Research Laboratory, and several fellowships (Intel, Microsoft, and the Computer  ...  Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  All processor simulators are execution-driven, cycle-level simulators; they model the processor pipelines and memory subsystems (including interthread contention for all structures in the memory hierarchy  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95  
We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/223982.224449 dblp:conf/isca/TullsenEL95 fatcat:rj3illxasbalhkiz4ygcsjsvdi

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 SIGARCH Computer Architecture News  
We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/225830.224449 fatcat:gtheubj4tbcqxokcmbrfoihxym

Data-Driven Multithreading Using Conventional Microprocessors

C. Kyriacou, P. Evripidou, P. Trancoso
2006 IEEE Transactions on Parallel and Distributed Systems  
This paper describes the Data-Driven Multithreading (DDM) model and how it may be implemented using off-the-shelf microprocessors.  ...  Data-Driven Multithreading is a nonblocking multithreading execution model that tolerates internode latency by scheduling threads for execution based on data availability.  ...  INTRODUCTION D ATA-DRIVEN Multithreading (DDM) is a nonblocking multithreading model based on the Decoupled Data Driven model of execution [1] , [2] .  ... 
doi:10.1109/tpds.2006.136 fatcat:qvgr6qn6qfcqhme72cl64hsx7q

IBM power5 chip: a dual-core multithreaded processor

R. Kalla, B. Sinharoy, J.M. Tendler
2004 IEEE Micro  
To the operating system, the physical processor core appears as if it is a symmetric multiprocessor containing two logical processors.  ...  Multithreading Conventional processors execute instructions from a single instruction stream. Despite microarchitectural advances, execution unit utilization remains low in today's microprocessors.  ...  Acknowledgments We thank Ravi Arimilli, Steve Dodson, and the entire Power5 team.  ... 
doi:10.1109/mm.2004.1289290 fatcat:s5epfknmljfwvkjotdl4n2fcpi

Hybrid multi-core architecture for boosting single-threaded performance

Jun Yan, Wei Zhang
2007 SIGARCH Computer Architecture News  
In this paper, we propose a compiler-driven heterogeneous multicore architecture, consisting of tightly-integrated VLIW (Very Long Instruction Word) and superscalar processors on a single chip, to automatically  ...  The scaling of technology and the diminishing return of complicated uniprocessors have driven the industry towards multicore processors.  ...  We develop a cycle-accurate model of the hybrid dual-core, based on the integration of the VLIW simulator from Trimaran [26] and the superscalar simulator -simplescalar [27] .  ... 
doi:10.1145/1241601.1241603 fatcat:vjzotxsbo5dtvc6oe6wcifxcie

Chip makers turn to multicore processors

D. Geer
2005 Computer  
Hyperthreading lets multithreaded software's threads execute in parallel on a single core, thereby improving performance.  ...  Intel provides a Threading Toolkit to help game and other software developers design multithreaded applications to be used on its new chips.  ... 
doi:10.1109/mc.2005.160 fatcat:aapc5jkpg5ft3mlrigzloacb4q
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