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An analysis of ADPLL applications in various fields

R. Dinesh, Ramalatha Marimuthu
2020 Indonesian Journal of Electrical Engineering and Computer Science  
In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator  ...  ADPLL consists of a phase detector, loop filter and digital controlled oscillator.  ...  [35] [33] [34] [37] [38] Phase detector Time to digital converter Snapshot Time to digital converter Frequency to digital converter Time to digital converter Time to digital converter  ... 
doi:10.11591/ijeecs.v18.i2.pp856-866 fatcat:f5syzddqhvchtiercom5f37sb4

GPS Synchronization of Smart Distributed Converters for Microgrid Applications

Tarek Youssef, Aboubakr Salem, Moataz Elsied, Augustin Mabwe, Mohammad Abido, Osama Mohammed
2018 Energies  
A global positioning system-based scheme is used to synchronize the carrier among the distributed converters.  ...  In this paper, a smart distributed DC/DC converter synchronization advanced technique and phase angle optimization algorithm are proposed using to reduce the DC bus overall ripple.  ...  All local controllers of DC-DC converters connected to the DC-bus will use ASA to control their local oscillator phase angles except the master converter where its phase offset will be set to zero.  ... 
doi:10.3390/en11040695 fatcat:o2tax7uuifgzzmgte6vsjmobwi

2019 Index IEEE Solid-State Circuits Letters Vol. 2

2019 IEEE Solid-State Circuits Letters  
., +, LSSC Oct. 2019 219-222 Digital phase locked loops A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter.  ...  ., +, LSSC Nov. 2019 264-267 Phase noise A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI.  ... 
doi:10.1109/lssc.2020.2967202 fatcat:ka56gc64uvfvbjddesloe5qmnu

A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX

David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Yu-Ling Lin, Ho-Hsiang Chen, Chewnpu Jou, Mau-Chung Frank Chang
2010 2010 Proceedings of ESSCIRC  
In addition, the LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. Central to the PLL performance is the design of a low-noise, mm-wave VCO with a 22.9% tuning range.  ...  The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF.  ...  However, when all 32 switches are off, the resistor-biased switch achieves an 7.5dB improvement in phase noise.  ... 
doi:10.1109/esscirc.2010.5619880 dblp:conf/esscirc/MurphyGWJXTWLCJ10 fatcat:7opxqb7f5beullog6l5xzf55km

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Mau-Chung Frank Chang
2011 IEEE Journal of Solid-State Circuits  
Central to the PLL performance is the design of a low-noise, wideband, mm-wave VCO with a 22.9% tuning range.  ...  The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with .  ...  Embedding this structure into all the mm-wave resonators enables fine digital tuning (down to a few fFs) and "first-time right" design promised by distributed element design.  ... 
doi:10.1109/jssc.2011.2143950 fatcat:4kwqupxerndltdgfzp7nrw63hm

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

Bryan Casper, Frank O'Mahony
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Index Terms-Clock distribution, clock recovery, high-speed I/O, phase-locked loops.  ...  The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level  ...  ACKNOWLEDGMENT The authors would like to thank J. Jaussi, M. Mansuri, G. Balamurugan, S. Shekhar, J. Kennedy, and R. Mooney for collaboration and helpful discussions.  ... 
doi:10.1109/tcsi.2008.931647 fatcat:m2zj3kalbvad7ee5m2znin4t7u

Digital Doppler-cancellation servo for ultra-stable optical frequency dissemination over fiber [article]

Shambo Mukherjee, Jacques Millo, Baptiste Marechal, Séverine Denis, Gwenhaël Goavec-Mérou, Jean-Michel Friedt, Yann Kersalé, Clément Lacroûte
2021 arXiv   pre-print
commercial board embedding a field programmable gate array, analog-to-digital and digital-to-analog converters.  ...  In this manuscript, we present a Doppler-cancellation setup based on a digital phase-locked loop for ultra-stable optical signal dissemination over fiber.  ...  The authors are with the FEMTO-ST Institute, univ. Bourgogne Franche-Comté, CNRS, ENSMM, 26 rue de l' Épitaphe, 25000 Besanc ¸on, France (e-mail: clement.lacroute@femto-st.fr). VI.  ... 
arXiv:2111.07891v1 fatcat:ayqimuvkg5e27jqgiwdkkql4yu

Evaluation of Quadrature Signal Generation Methods with Reduced Computational Resources for Grid Synchronization of Single-Phase Power Converters through Phase-Locked Loops

Paula Lamo, Alberto Pigazo, Francisco J. Azcondo
2020 Electronics  
Low-cost single-phase grid connected converters require synchronization with the grid voltage to obtain a better response and protection under diverse conditions, such as frequency perturbations and distortion  ...  Phase-locked loops (PLLs) have been used in this scenario.  ...  All the authors were involved in preparing the final version of this manuscript. All authors have read and agreed to the published version of the manuscript.  ... 
doi:10.3390/electronics9122026 fatcat:nv6hycb4yjagdorvr6behf63hy

A Wide-Tracking Range Clock and Data Recovery Circuit

Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon
2008 IEEE Journal of Solid-State Circuits  
The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution.  ...  A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise  ...  Min Gyu Kim, and all the members of Intel Circuit Research Labs Signalling team for useful discussions and critical feedback.  ... 
doi:10.1109/jssc.2007.914290 fatcat:f36tl7sghvaapaepxgn4czwwtu

A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

Pengfei Li, Deepak Bhatia, Lin Xue, Rizwan Bashirullah
2011 IEEE Journal of Solid-State Circuits  
This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters.  ...  We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%.  ...  A hysteretic controlled dc-dc buck converter with the proposed D-PLL based synchronization scheme was implemented in 130 nm 1.2 V digital CMOS process.  ... 
doi:10.1109/jssc.2011.2139550 fatcat:sqkhsjtpsbckdfxfxm4squhy4m

Clock Signal in Electronic Systems [chapter]

2012 Nanometer Frequency Synthesis Beyond the Phase-Locked Loop  
the transitions embedded in the data stream with a PLL.  ...  There are several styles in the PLL -based approach: integer -N PLL, fractional -N PLL, sigma -delta fractional -N PLL, and all digital PLL ( ADPLL ).  ...  In other words, if there is a clock spur at − f s , we can also fi nd spurs at − f s + f c .  ... 
doi:10.1002/9781118347959.ch1 fatcat:lmdixx4ipndynbdlp2lcedmtoq

High Speed On-Chip Signal Generation for Debug and Diagnosis

Tsung-Yen Tsai, Sadok Aouini, Gordon Walter Roberts
2012 Journal of electronic testing  
An arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency  ...  In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency).  ...  Likewise a digital-to-frequency converter (DFC) converts a digital code to a corresponding instantaneous frequency.  ... 
doi:10.1007/s10836-012-5289-0 fatcat:xhv3vr7vqrdwtoijger26eeq7m

All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter

Moon Seok Kim, Yong-Bin Kim, Kyung-Ki Kim
2012 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)  
An All-Digital Phase-Locked Loop (ADPLL) design is proposed to achieve short locking time using a circuitry of the LPI-TDC based on tri-state inverter.  ...  The objective of the thesis is to design a novel ADPLL with local passive interpolation time-to-digital (LPI-TDC) based on a tri-state inverter for clock synchronization, clock recovery, and noise and  ...  Using the theory and circuits developed, a fully digital All-digital phase-locked loop with a novel local passive interpolation time-to-digital converter (LPI-TDC) based on a tri-state inverter is designed  ... 
doi:10.1109/mwscas.2012.6292023 dblp:conf/mwscas/KimKK12 fatcat:ngveefsr75ch3op7xjm3lf4ggi

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Wanghua Wu, Robert Bogdan Staszewski, John R. Long
2014 IEEE Journal of Solid-State Circuits  
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed.  ...  Index Terms-60 GHz, all-digital phase-locked loop (ADPLL), CMOS technology, digital calibration, FMCW radar, mm-wave frequency synthesizer, multi-rate two-point frequency modulation. John R.  ...  Straver, A. Akhnoukh, and M. Spirito for measurement support. They also thank Integrand Software for providing the EM simulation tool, EMX.  ... 
doi:10.1109/jssc.2014.2301764 fatcat:rlafztretzdslovw46qwr263oa

A single-chip x-band chirp radar MMIC with stretch processing

Jianjun Yu, Feng Zhao, Joseph Cali, Desheng Ma, Xueyang Geng, Fa Foster Dai, J. David Irwin, Andre Aklian
2012 Proceedings of the IEEE 2012 Custom Integrated Circuits Conference  
The radar chip, including receiver, transmitter, quadrature DDS, phase-locked loop (PLL) and analog to digital converter (ADC), has been implemented in a 0.13μm BiCMOS technology.  ...  A wide-tuning PLL frequency synthesizer is integrated to generate the local oscillator (LO) signals as well as the clock signal for the DDS and ADC.  ...  The authors would like to acknowledge Jonathan Corriveau and Geoffrey Goldman for funding and managing this project.  ... 
doi:10.1109/cicc.2012.6330617 dblp:conf/cicc/YuZCMGDIA12 fatcat:l67gdhb5c5di5aua2eda2kmbcu
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