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A Critical Review of Single Phase Inverter Grid Synchronization Topologies

Amit ARIAL, Ali HELLANY, Mahmood NAGRIAL, Jamal RIZK
2017 DEStech Transactions on Environment Energy and Earth Science  
Digital filter based on Kalman filtering and Fourier analysis can track grid voltages very quickly.  ...  One solution to this problem is using a FIR (Finite Impulse Response) Filter.  ...  It is realized in the literature using digital FIR (finite impulse response filter).Harmonic distortion is an issue with low order FIR filter.  ... 
doi:10.12783/dteees/peem2016/5012 fatcat:5orwccbpobb43fgvtorahprisy

Fpga Based Sdr For Dpll Application

NIKITA KATOLE, SHWETA THAKUR
2017 Zenodo  
At the modulator and demodulator sections, a Digital Frequency Generator (DFG) is applied for generating the carrier wave by exploiting the quarter wave symmetry of sine or cosine waves with dynamic range  ...  To design and develop a system on chip reconfigurable modules Field Programmable Gate Array (FPGA) provides a way with high performance.  ...  FINITE IMPULSE RESPONSE FILTER: A finite impulse response filter (FIR) is said to a filter which has a finite duration impulse response and it settles to zero in finite time.  ... 
doi:10.5281/zenodo.1452487 fatcat:ri6lh67q35eh3fhyydqwc2bjgu

A digital asynchronous sample-rate converter for digital video signals

D. Wenzel, J. Speidel
2000 IEEE transactions on consumer electronics  
In this paper, a new all-digital asynchronous sample-rate converter (SRC) for video signals with an effective resolution of 12 bits using digital signal processing is presented.  ...  The architecture of the digital SRC which is optimized for an implementation with small memory and low processing power is shown in detail.  ...  response, % h = resulting impulse response. % 1.  ... 
doi:10.1109/30.826400 fatcat:x5ekverhrnbvjdaxq2y6o6bjfm

Fully integrated standard cell digital PLL

T. Olsson, P. Nilsson
2001 Electronics Letters  
.: 'A hysteresis-based chaotic circuit: dynamics and applications', Int.  ...  To achieve a faster impulse response and thereby a shorter lock time for the PLL, the output from the counters is multiplied by 4 whenever both counters are saturated.  ...  Since the counters are only three bit wide, they will often saturate during the initial phase of an impulse response.  ... 
doi:10.1049/el:20010160 fatcat:blgchxnq4zetlb2atftyxdfiu4

Systematic realization of a class of hysteresis chaotic oscillators

A. S. Elwakil, M. P. Kennedy
2000 International journal of circuit theory and applications  
.: 'A hysteresis-based chaotic circuit: dynamics and applications', Int.  ...  To achieve a faster impulse response and thereby a shorter lock time for the PLL, the output from the counters is multiplied by 4 whenever both counters are saturated.  ...  Since the counters are only three bit wide, they will often saturate during the initial phase of an impulse response.  ... 
doi:10.1002/1097-007x(200007/08)28:4<319::aid-cta107>3.0.co;2-z fatcat:peuhrwbbizga3njnm4ulkf5o5e

A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

Bo Zhou
2014 The Scientific World Journal  
A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters.  ...  A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity.  ...  To further simplify filters, the proposed 3rd-order inverse-FIR and 4th-order inverse-( ) filters are combined together by employing a 7th-order infinite-impulse-response (IIR) digital filter with a high-pass  ... 
doi:10.1155/2014/521717 pmid:24719578 pmcid:PMC3956518 fatcat:cdbfu2vebjbife4yuqcuaw7iem

Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Socrates D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic
2011 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.  ...  In this paper a discrete-time, linear, periodically time-variant integer-PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop  ...  A similar response is produced by a voltage impulse on the VCO supply.  ... 
doi:10.1109/tcsi.2010.2097694 fatcat:2usmiwu4lfarxl4vwgaws72vw4

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators

Sudhakar Pamarti, Jared Welz, Ian Galton
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
An analysis of the quantization noise introduced by a widely-used class of single-quantizer digital delta-sigma (16) modulators with low-level, 1-bit dither is presented.  ...  Several of the most commonly-used digital 16 modulators are shown to satisfy the conditions.  ...  Then, the impulse response of satisfies the conditions of part (ii) of the Theorem 1 for , where is a positive integer. Proof: The impulse response of is .  ... 
doi:10.1109/tcsi.2006.887616 fatcat:trvuw54rjrexppakqomrsbd4su

Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design

Woogeun Rhee, Ni Xu, Bo Zhou, Zhihua Wang
2013 JSTS Journal of Semiconductor Technology and Science  
This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ∆Σ modulation technique and a finite-impulse response (FIR) filtering method.  ...  Spur generation and nonlinearity issues in the ∆Σ fractional-N PLLs are discussed with simulation and hardware results.  ...  FIR-Embedded ∆Σ Modulation The semi-digital approach based on a finite-impulse response (FIR) filtering method offers moderate quantization noise reduction without using the DAC [22] [23] [24] [25] [26  ... 
doi:10.5573/jsts.2013.13.2.170 fatcat:uuo5o7hg55bo5ltqfcirwql34a

Discrete-time, cyclostationary phase-locked loop model for jitter analysis

Socrates D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic
2009 2009 IEEE Custom Integrated Circuits Conference  
Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3 rd -order PLL.  ...  Timing jitter is one of the most significant phaselocked loop characteristics, with high impact on performance in a range of applications.  ...  The main difference with the VCO case is that the noise accumulates over a finite period of time.  ... 
doi:10.1109/cicc.2009.5280745 dblp:conf/cicc/VamvakosSN09 fatcat:odrzxdrucbalrnyy2xsk3mkf54

LSB Dithering in MASH Delta–Sigma D/A Converters

Sudhakar Pamarti, Ian Galton
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
white and uncorrelated with the input.  ...  Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta-sigma (16) modulator in a multistage digital 16 modulator is asymptotically  ...  A. Swaminathan and Dr. J. Welz for valuable discussions regarding this paper.  ... 
doi:10.1109/tcsi.2006.888780 fatcat:ioafxhxwbnalbo3vfuhux3ukyi

A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer

D.R. McMahill, C.G. Sodini
2002 IEEE Journal of Solid-State Circuits  
The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation.  ...  The PLL, including 1.8-GHz voltage controlled oscillator (VCO), 6-1 modulator, and automatic calibration circuit, has been implemented in a 0.6-m BiCMOS integrated circuit.  ...  If a finite impulse response (FIR) filter is used, the relatively narrow 5 transition band will lead to a large number of filter coefficients.  ... 
doi:10.1109/4.974542 fatcat:nsoeqxjctnddhjxfnbg3wauufq

A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis

M.H. Perrott, M.D. Trott, C.G. Sodini
2002 IEEE Journal of Solid-State Circuits  
A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations.  ...  The framework is used to analyze the noise performance of a custom 6-1 synthesizer implemented in a 0.6-m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency  ...  Our justification for the impulse approximation is heuristic-each PFD output pulse has much smaller width than the loop filter impulse response, and therefore acts like an impulse when the two are convolved  ... 
doi:10.1109/jssc.2002.800925 fatcat:gatn6eit5fhe7m3qwtntplkige

Analysis of PLL clock jitter in high-speed serial links

P. Kumar Hanumolu, B. Casper, R. Mooney, Gu-Yeon Wei, Un-Ku Moon
2003 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response.  ...  A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.  ...  Therefore, we characterize a channel by its impulse response.  ... 
doi:10.1109/tcsii.2003.819121 fatcat:3uoglpaphzd6ler66pghbczpx4

Evaluation of Quadrature Signal Generation Methods with Reduced Computational Resources for Grid Synchronization of Single-Phase Power Converters through Phase-Locked Loops

Paula Lamo, Alberto Pigazo, Francisco J. Azcondo
2020 Electronics  
Low-cost single-phase grid connected converters require synchronization with the grid voltage to obtain a better response and protection under diverse conditions, such as frequency perturbations and distortion  ...  This paper describes a set of quadrature signal generators for single-phase PLLs; compares the performances by means of simulation tests considering diverse operation conditions of the electrical grid;  ...  Oscillator DSO Distribution system operators DSC Delay Signal Compensation DSP Digital signal processor D PLL PLL based on derivative EPLL Enhanced Phase-Locked Loop FIR Finite Impulse Response  ... 
doi:10.3390/electronics9122026 fatcat:nv6hycb4yjagdorvr6behf63hy
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