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Performance Comparison for Different Configurations of SRAM Cells
english
2015
International Journal of Innovative Research in Science, Engineering and Technology
english
Preserved Fulltext
In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. ...
Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today's memory technology. ...
Besides this its write time is higher and this cell occupies 30% more space than a conventional 6T SRAM cell [9] . 9T SRAM cell has high read noise margin, write noise margin and also has small write ...
doi:10.15680/ijirset.2015.0401018
fatcat:zzms5e7qwvg67ncbnujuxd73hu
Nanowire Volatile RAM as an Alternative to SRAM
[article]
2014
arXiv
pre-print
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In this paper, we elaborate more on NWRAM circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs ...
Our results show the 10T-NWRAM to be 2x faster and 35x better in terms of leakage when compared to high performance gridded 8T-SRAM design. ...
Fig. 10 shows 10T-NWRAM write time to be almost 2x faster in comparison to HP 6T-SRAM and HP 8T-SRAM, and more than 4.5x faster when compared to LP 6T-SRAM and LP 8T-SRAM. ...
arXiv:1404.0615v1
fatcat:lef64uy7onhuhelddz7wmgb3oe
Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design
2020
Journal of Nanotechnology
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GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. ...
This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. ...
On the whole, both GNRFET and FinFET-based SRAM designs outperform the MOSFET-based design. Table 4 shows the noise margin of MOSFET-, FinFET-, and GNRFET-based 6T SRAM cells and 8T SRAM cells. ...
doi:10.1155/2020/7608279
fatcat:djwxjd5q5nbsjbqqwmowy2fmvu
Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches
[chapter]
2020
Embedded Systems
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In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and ...
The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor ...
Fig. 2 2 Schematic diagram of 6T and 8T SRAM cell, where WL = word-line, BL = bit-line and RL = read-line. (a) 6T cell design. ...
doi:10.1007/978-3-030-52017-5_13
fatcat:i4k2wohtlvgkjb2fpm2br4eqny
Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
2012
IEEE Transactions on Circuits and Systems - II - Express Briefs
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In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. ...
In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. ...
In a thin-cell layout approach, the SRAM bit-cell area is dominated by the contact and the diffusion spacing. ...
doi:10.1109/tcsii.2012.2198984
fatcat:vkplkqrzdffc7difvhothsxn6e
Low power/ Low Voltage Cross Coupled SRAM – Based on Schmitt Trigger
2013
IOSR Journal of VLSI and Signal processing
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In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual ...
the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results ...
Figure 5: Layout Design of 8T-SRAM Power Analysis of 8T-SRAM Design
Table1. Power/voltage consumption comparison Sl. ...
doi:10.9790/4200-0323034
fatcat:jedmoq75wvd7vmc6gjj6t7chve
Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation
2019
Electronics
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In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. ...
Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/electronics8060611
fatcat:dkiwerwbsjh5tc5vd3tvfzwtri
A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories
2015
Journal of Low Power Electronics and Applications
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Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc ...
Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations ...
Author Contributions FinFET devices are designed and simulated by Shuang Chen and Yanzhi Wang. Circuit simulation are done by Alireza Shafaei and Yanzhi Wang. ...
doi:10.3390/jlpea5030165
fatcat:4jw4dqwjljeixg7xxfvdffotm4
Approximate compressed sensing
2014
Proceedings of the 2014 international symposium on Low power electronics and design - ISLPED '14
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We propose a digital architecture featuring a hybrid memory (6T-SRAM/SCMEM cells) designed to control perturbations on specific data structures. ...
Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. ...
A standard cell-based memory was designed and fabricated in a 40 nm CMOS technology. For comparison reason, also a commercial 6T memory was fabricated on the same chip. ...
doi:10.1145/2627369.2627629
dblp:conf/islped/BortolottiMBASAVB14
fatcat:qcumlgbwt5gfrjbymnfrrdsrz4
Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
2014
IEEE transactions on nanotechnology
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We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. ...
In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. ...
ACKNOWLEDGMENT The authors would like to thank the valuable help of L. Tsung-Te in understanding the effects of strain and IMEC Belgium for the compact models of the transistors. ...
doi:10.1109/tnano.2014.2354073
fatcat:ak3u2bvxubhyjc7to6nttyzthe
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
2014
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. ...
This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply ...
ACKNOWLEDGMENT The authors are grateful to CIC, ITRI, NSC, and MOEA, Taiwan, for project support and Taiwan Semiconductor Manufacturing Company (TSMC) for the University Shuttle Program. ...
doi:10.1109/tcsi.2014.2332267
fatcat:tiqbxrp4szditpvhkrxo3cmvye
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
2018
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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2017 pre-print arXiv:1712.05096v1 fatcat:rg73x7weszdjfd5sns4vvjvve4Other Versions
Silicon-based Static Random Access Memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-art computing platforms. ...
and the 8^+T Differential cell. ...
However, the 6T-SRAM bit-cells have a coupled read-write path that imposes conflicting constraints on the design of the 6T cell, thereby raising issues of read-disturb failures. ...
doi:10.1109/tcsi.2018.2848999
fatcat:mzsquwbfm5ew7nzkeynd6i3die
Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes
2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
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This paper proposes a novel, hybrid-operation (high Vcc, ultralow Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells ...
Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 C) required for new market segments such as body, urban life and environment monitoring ...
ACKNOWLEDGEMENTS This work has been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2012-34557, HiPEAC and the UPC under grant FPI-UPC. ...
doi:10.7873/date.2013.193
dblp:conf/date/MaricAV13
fatcat:kukbebx23bfmzg4uqpexmltnpu
Synergistic HW/SW Approximation Techniques for Ultra-Low-Power Parallel Computing
2016
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work we propose a novel HW/SW approach to design energy-efficient ultralow-power systems which combine the key ideas of approximate computing and hybrid memory systems featuring both SCM and 6T-SRAM ...
Ultra-low-power embedded systems have recently started the move to multi-core designs. ...
ACKNOWLEDGMENT This work is supported by the European FP7 ERC Advanced project MULTITHERMAN (g.a. 291125) and by IcySoC and YINS RTD projects, evaluated by the Swiss NSF and funded by Nano-Tera.ch with ...
doi:10.1109/tcad.2016.2633474
fatcat:drbmba5xvbfubh2bdtrawwcnre
Adapting the columns of storage components for lower static energy dissipation
2013
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
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We analyzed the content distribution of columns of SRAM arrays and based on the majority of the content, the body-bias of transistors are changed to reduce the static energy dissipation of these SRAM arrays ...
Static energy dissipation caused by leakage currents is increasing with every new technology and large SRAM arrays are the main source of the leakage current. ...
SRAM BITCELL DESIGN SRAM bitcell was previously designed with six transistors and called as the 6T-SRAM bitcell. ...
doi:10.1109/vlsi-soc.2013.6673279
dblp:conf/vlsi/AykenarOSE13
fatcat:ksvejd7ymvgpzohkehiphmk73u
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