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A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton

Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA
2012 IEICE transactions on information and systems  
Hiroki NAKAHARA †a) , Tsutomu SASAO †b) , and Munehiro MATSUURA †c) , Members SUMMARY This paper shows a design method for a regular expression matching circuit based on a decomposed automaton.  ...  To implement a regular expression matching circuit, first, we convert a regular expression into a non-deterministic finite automaton (NFA).  ...  Hiroaki Yoshida encouraged us to participate the design contest. The hard work of the organizers of the MEMOCODE2010 HW/SW co-design contest is also appreciated.  ... 
doi:10.1587/transinf.e95.d.364 fatcat:6j2xgsld6jcvljnnafejtndfsy

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2012 Microprocessors and microsystems  
This paper shows a compact realization of regular expression matching circuits on FPGAs.  ...  First, the given regular expression is converted into a non-deterministic finite automaton (NFA) by the modified McNaughton-Yamada method.  ...  This research is supported in part by the grant of Regional Innovation Cluster Program (Global Type, 2nd Stage). Discussion with Prof. J. T. Butler was quite useful.  ... 
doi:10.1016/j.micpro.2012.05.009 fatcat:54bqe2e4j5e7ndjjlm3nywfmky

A regular expression matching using non-deterministic finite automaton

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
2010 Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)  
A regular expression matching circuit is performed as follows: First, the given regular expressions are converted into a non-deterministic finite automaton (NFA).  ...  We loaded 140 regular expressions of the MEM-OCODE 2010 design contest on Terasic Corp. DE3 prototyping board (FPGA: Altera's Stratix III).  ...  Hiroaki Yoshida encouraged us to participate the design contest. The authors appreciate the organizer's hard work to prepare for the contest.  ... 
doi:10.1109/memcod.2010.5558621 dblp:conf/memocode/NakaharaSM10 fatcat:5ajezm7y4zbr3gymlgl37skaa4

A Real-time Updatable FPGA-based Architecture for Fast Regular Expression Matching

Qiu Tang, Lei Jiang, Xin-xing Liu, Qiong Dai
2014 Procedia Computer Science  
Secondly, in order to support large-scale and complex semantic regular expression rule sets, we design an improved run-length encoding (iRLE) algorithm based on FPGA to reduce the DFA's storage space.  ...  In this paper, we firstly propose a new architecture on FPGA supporting real-time update FSM, and design a special protocol for this update.  ...  Prasanna [1] firstly implement regular expression matching on FPGA using nondeterministic finite automata. Their design special algorithm to compile regular expressions into VHDL described circuit.  ... 
doi:10.1016/j.procs.2014.05.336 fatcat:br5c4rbr7vgezjxsgztojxijka

Reasoning about GSTE Assertion Graphs [chapter]

Alan J. Hu, Jeremy Casas, Jin Yang
2003 Lecture Notes in Computer Science  
In particular, GSTE specifications are given as assertion graphs, a variety of ∀-automata, and although an efficient model-checking algorithm exists to verify whether a circuit model obeys a specification  ...  Generalized symbolic trajectory evaluation (GSTE) is a new modelchecking approach that combines the industrially-proven scalability and capacity of classical symbolic trajectory evaluation with the expressive  ...  was inspired by efficient methods for generating circuits from regular expressions [15, 14, 11] .  ... 
doi:10.1007/978-3-540-39724-3_17 fatcat:rfiuhi7dyrdpxbratumkj42eqi

Sequential Relational Decomposition

Dror Fried, Axel Legay, Joël Ouaknine, Moshe Y. Vardi
2018 Proceedings of the 33rd Annual ACM/IEEE Symposium on Logic in Computer Science - LICS '18  
Our results indicate that the intuitive idea of decomposition as a system-design approach requires further investigation.  ...  The concept of decomposition in computer science and engineering is considered a fundamental component of computational thinking and is prevalent in design of algorithms, software construction, hardware  ...  A language is also regular if and only if it can be described by a regular expression. We define the size of the automaton A as |Q | + |Σ| + |δ | and denote this size by |A|.  ... 
doi:10.1145/3209108.3209203 dblp:conf/lics/FriedLOV18 fatcat:cyta6riskrhsxcuvbqp4fx5iuu

Scalable specification mining for verification and diagnosis

Wenchao Li, Alessandro Forin, Sanjit A. Seshia
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
Given an execution trace, we mine recurring temporal behaviors in the trace that match a set of pattern templates.  ...  We demonstrate the effectiveness of our approach on industrial-size examples by mining specifications from traces of over a million cycles in a few minutes and use them to successfully localize errors  ...  The authors acknowledge the support of the Gigascale Systems Research Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity  ... 
doi:10.1145/1837274.1837466 dblp:conf/dac/LiFS10 fatcat:3qy7mzlvd5afxcldlf5fciapri

Self-timed Reinforcement Learning using Tsetlin Machine [article]

Adrian Wheeldon, Alex Yakovlev, Rishad Shafik
2021 arXiv   pre-print
The work builds on previous design of the inference hardware, and includes an in-depth breakdown of the automaton feedback, probability generation and Tsetlin automata.  ...  We present a hardware design for the learning datapath of the Tsetlin machine algorithm, along with a latency analysis of the inference datapath.  ...  We are also grateful to colleague Thomas Bunnam for fruitful discussions on ROs and RNG techniques. The authors would like to acknowledge the funding support from EPSRC IAA grant: Whisperable.  ... 
arXiv:2109.00846v1 fatcat:63iyjzybkvdbrbv4pe4trhfmva

Reverse engineering circuits using behavioral pattern mining

Wenchao Li, Zach Wasson, Sanjit A. Seshia
2012 2012 IEEE International Symposium on Hardware-Oriented Security and Trust  
The proposed approach is based on mining interesting behavioral patterns from the simulation traces of a gate-level netlist, and representing them as a pattern graph.  ...  We demonstrate the effectiveness of our approach on publicly-available circuits.  ...  In this paper, we mainly write specifications using a combination of LTL and regular expressions, employing the following four patterns: 1.  ... 
doi:10.1109/hst.2012.6224325 dblp:conf/host/LiWS12 fatcat:6fzvx2gnvjbl7lz7ma5c2hiusm

Decomposition of Constraint Automata [chapter]

Bahman Pourvatan, Marjan Sirjani, Farhad Arbab, Marcello M. Bonsangue
2012 Lecture Notes in Computer Science  
Reo is a coordination language that can be used to model different systems. Constraint automata form a formal semantics for Reo connectors based on a co-algebraic model of streams.  ...  This property helps to partition and decompose a constraint automaton, a process which can be utilized to synthesize Reo circuits from constraint automata, automatically.  ...  constraint automaton A 1 , A 2 , and B, where B = A 1 A 2 : decompose a constraint automaton A based on a given constraint automaton B, we only compute the product of the completion of Υ (A) with the  ... 
doi:10.1007/978-3-642-27269-1_14 fatcat:tq6gfv4divfcpkzjjigwy62fme

Sequential Relational Decomposition [article]

Dror Fried, Axel Legay, Joël Ouaknine, Moshe Y. Vardi
2022 arXiv   pre-print
Our results indicate that the intuitive idea of decomposition as a system-design approach requires further investigation.  ...  The concept of decomposition in computer science and engineering is considered a fundamental component of computational thinking and is prevalent in design of algorithms, software construction, hardware  ...  Based on her understanding of the problem, the decomposer has to make a decision on how to decompose a given problem, for example, by meeting certain constraints on the size of the sub-problems, or constraints  ... 
arXiv:1903.01368v6 fatcat:pflwg6rzenebba4ahcfhflgyhe

Self-timed Reinforcement Learning using Tsetlin Machine

Adrian Wheeldon, Alex Yakovlev, Rishad Shafik
2021 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)  
The work builds on previous design of the inference hardware, and includes an in-depth breakdown of the automaton feedback, probability generation and Tsetlin automata.  ...  We present a hardware design for the learning datapath of the Tsetlin machine algorithm, along with a latency analysis of the inference datapath.  ...  We are also grateful to colleague Thomas Bunnam for fruitful discussions on ROs and RNG techniques. The authors would like to acknowledge the funding support from EPSRC IAA grant: Whisperable.  ... 
doi:10.1109/async48570.2021.00014 fatcat:7i5oloiiirapvmawgkmnzjzaqe

Sequential Relational Decomposition

Dror Fried, Axel Legay, Joël Ouaknine, Moshe Y. Vardi
2022 Logical Methods in Computer Science  
Our results indicate that the intuitive idea of decomposition as a system-design approach requires further investigation.  ...  The concept of decomposition in computer science and engineering is considered a fundamental component of computational thinking and is prevalent in design of algorithms, software construction, hardware  ...  A language is also regular if and only if it can be described by a regular expression. We define the size of the automaton A as |Q| + |Σ| + |δ| and denote this size by |A|.  ... 
doi:10.46298/lmcs-18(1:37)2022 fatcat:ykvmqayal5bthjcdb6dmbxpqpe

Efficient Decompositional Model Checking for Regular Timing Diagrams [chapter]

Nina Amla, E. Allen Emerson, Kedar S. Namjoshi
1999 Lecture Notes in Computer Science  
Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of signals.  ...  This graphical notation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called Regular Timing Diagrams (RTD's).  ...  Introduction The design of hardware systems includes the specification of timing behavior for circuit components.  ... 
doi:10.1007/3-540-48153-2_7 fatcat:mja3q4hq5fd5fonn4urrgeybvm

A formal approach to designing delay-insensitive circuits

Jo C. Ebergen
1991 Distributed computing  
A method for designing delay-insensitive circuits is presented based on a simple formalism.  ...  The communication behavior of a circuit with Its envlronmenf is speclfied by a regular expresslon-llke program.  ...  ACKNOWLEDOEMENTS Martin Rem, Huub Sehols, and the members of the Eindhoven VLSI Qub are gratefully acknowledged for their suggestions of improvement on earlier drafts of this paper.  ... 
doi:10.1007/bf02252954 fatcat:txndagpemvghrchrcoa2ee274m
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