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Custom parallel caching schemes for hardware-accelerated image compression

Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2008 Journal of Real-Time Image Processing  
This memory sub-system is made up of a custom parallel cache and a scratchpad memory.  ...  These performance improvements are more pronounced for image sequences exhibiting greater inter-frame movements.  ...  access pattern is unknown at design time.  ... 
doi:10.1007/s11554-008-0082-0 fatcat:cgyfs2g4ubecxbuc4xesyacusm

Rhymes: A shared virtual memory system for non-coherent tiled many-core architectures

King Tin Lam, Jinghao Shi, Dominic Hung, Cho-Li Wang, Zhiquan Lai, Wangbin Zhu, Youliang Yan
2014 2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS)  
Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical memory (SPM) and scope consistency for pages in percore private memory.  ...  This paper presents a shared virtual memory (SVM) system, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid memory architectures.  ...  ., Ltd. for their kind support of the SCC platform in their Wuxi data centers for this work.  ... 
doi:10.1109/padsw.2014.7097807 dblp:conf/icpads/LamSHWLZY14 fatcat:sadkzvqywjepzenwnp32nr65fi

Page Classifier and Placer: A Scheme of Managing Hybrid Caches [chapter]

Xin Yu, Xuanhua Shi, Hai Jin, Xiaofei Liao, Song Wu, Xiaoming Li
2014 Lecture Notes in Computer Science  
Hybrid cache architecture (HCA), which uses two or more cache hierarchy designs in a processor, may outperform traditional cache architectures because no single memory technology can deliver the optimal  ...  We propose a new HCA approach that enables OS to be aware of underlying hybrid cache architecture and to control data placement, at OS page level, onto difference cache regions.  ...  Therefore, this design is almost agnostic to the design of HCA (hybrid cache architecture), which makes it scalable for different HCAs.  ... 
doi:10.1007/978-3-662-44917-2_2 fatcat:2kfksbpiszejrjefjbtdss2u4e

MN-MATE

Kyu Ho Park, Woomin Hwang, Hyunchul Seok, Chulmin Kim, Dong-jae Shin, Dong Jin Kim, Min Kyu Maeng, Seong Min Kim
2015 ACM Journal on Emerging Technologies in Computing Systems  
MN-MATE: Elastic resource management of manycores and a hybrid memory hierarchy for a cloud node. ACM  ...  A guest OS reduces energy consumption with small performance loss based on the NVRAM-aware data placement policy and the hybrid page cache.  ...  Hybrid Page Cache Hybrid main memory of M2 NVRAM and M2 DRAM also gives each guest OS a need to manage data placements for its own page cache.  ... 
doi:10.1145/2701429 fatcat:t7amqrizzbhszookhhodwfghe4

Page placement in hybrid memory systems

Luiz E. Ramos, Eugene Gorbatov, Ricardo Bianchini
2011 Proceedings of the international conference on Supercomputing - ICS '11  
In this paper, we propose a new hybrid design that features a hardware-driven page placement policy.  ...  For these reasons, researchers have proposed memory systems that combine a small amount of DRAM and a large amount of PCM.  ...  Acknowledgments We thank Rekha Bachwani, Kien Le, and Wei Zheng for their help in the early stages of this work.  ... 
doi:10.1145/1995896.1995911 dblp:conf/ics/RamosGB11 fatcat:36lwkzitubd5hj5pkusarh4hma

Power Conserving and Access Efficient Indexes for Wireless Computing [chapter]

Dik Lun Lee, Qinglong Hu, Wang-Chien Lee
2000 Information Organization and Databases  
Moreover, we introduce two access efficient indexing methods, cache schedule and integrated signature, for a wireless data dissemination system that incorporates both of broadcast and on-demand services  ...  Among them, hybrid index is the best choice for improving power efficiency under both scenarios of single and multiple attributes based queries.  ...  For a static hybrid channel allocation, the data access method depends on the availability of indexing methods.  ... 
doi:10.1007/978-1-4615-1379-7_18 fatcat:3dqlxlgggzgqrpkvirrlsu7p3e

Pervasive data access in wireless and mobile computing environments

Ken C. K. Lee, Wang-Chien Lee, Sanjay Madria
2007 Wireless Communications and Mobile Computing  
With wireless connections, users can access information at PDA), fosters a new class of mobile applications such as just-in-time stock trading, news services, and mobile games.  ...  One of the research focus is on pervasive data access.  ...  Their cost models for access time and tuning time were given. For simple signatures, a signature frame is broadcast before its corresponding data frame.  ... 
doi:10.1002/wcm.424 fatcat:g65i5ovz55gkloi24oakwsknxu

Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC

Felipe M. Sampaio, Bruno Zatt, Muhammad Shafique, Jorg Henkel, Sergio Bampi
2018 IEEE transactions on circuits and systems for video technology (Print)  
A hybrid scratchpad video memory (Hy-SVM) for energy-efficient Tiles-parallelized High-Efficiency Video Coding (HEVC) is presented herein.  ...  We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the SPMs parameters.  ...  To this end, we designed a hybrid scratchpad video memory architecture (Hy-SVM) that relies on joint inter-and intra-Tiles 2 data reuse and hybrid memory design, based on combined Static Random Access  ... 
doi:10.1109/tcsvt.2018.2870825 fatcat:uwwx5efrvjfxrmc3phr76zu3r4

Improving disk bandwidth-bound applications through main memory compression

Vicenç Beltran, Jordi Torres, Eduard Ayguadé
2007 Proceedings of the 2007 workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '07  
The main benefit of this technique is the reduction of slow disk I/O operations, thus improving data access latency and saving disk I/O bandwidth.  ...  In this paper we implement and evaluate in the Linux OS a full SMP capable main memory compression subsystem that takes advantage of a current multicore and multiprocessor system to increase the performance  ...  The Hybrid connector follows the architecture design explained in [7] .  ... 
doi:10.1145/1327171.1327178 fatcat:lpa6zvtvivg7blu3pazmpfzvwm

Article summaries

A.R. Hurson, K.M. Kavi, B. Shirazi, B. Lee
1996 IEEE Parallel & Distributed Technology Systems & Applications  
Designers can increase architectural support for instruction-level parallelism to absorb such a massive hardware capacity; examples are superscalar and superpipeline machmes.'  ...  processing, which offers new alternatives in computer architecture design, and analyze cache memo y 's application to the dataflow environment. urrent microelectronics technology has enabled chip capacity  ...  INSTRUCTION CACHE DESIGN PERAND CACHE DESIGN W e examined the use of two-level set associativity for operand cache memories, which is similar to the DFM-I1 design.* At the first level, we partitioned  ... 
doi:10.1109/88.544436 fatcat:gghokp44izf65ocixorvsnjix4

What is a good buffer cache replacement scheme for mobile flash storage?

Hyojun Kim, Moonkyung Ryu, Umakishore Ramachandran
2012 Performance Evaluation Review  
To answer this question, we first expose the limitations of current buffer cache performance evaluation methods, and propose a novel evaluation framework that is a hybrid between trace-driven simulation  ...  Armed with this knowledge, we propose a new buffer cache replacement scheme called SpatialClock.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their insightful comments, which helped us tremendously in revising the manuscript.  ... 
doi:10.1145/2318857.2254786 fatcat:db5bup3btnfzfnp7tgtlg5u3bq

Reference Pattern-Aware Instant Memory Balancing for Consolidated Virtual Machineson Manycores

Woomin Hwang, Ki-Woong Park, Kyu Ho Park
2015 IEEE Transactions on Parallel and Distributed Systems  
Consequently, HD2 significantly reduces the time taken to reallocate memory with a low overhead and enhances the value of additional memory for the recipient VMs.  ...  The scheduling of the VMs and their VCPUs generates the delay, the dirtiness of the candidate pages for balancing makes the delay fluctuated, and a conflict of two reclamation policies between the guest  ...  system for manycores and a hybrid memory hierarchy, as shown in Fig. 1 .  ... 
doi:10.1109/tpds.2014.2340854 fatcat:ebzbjkzx7va5ddpcdhmcoeqdzy

HAC

Miguel Castro, Atul Adya, Barbara Liskov, Andrew C. Meyers
1997 Proceedings of the sixteenth ACM symposium on Operating systems principles - SOSP '97  
This paper presents HAC, a novel technique for managing the client cache in a distributed, persistent object storage system.  ...  Thus we show that our hybrid, adaptive approach is the cache management technique of choice for distributed, persistent object systems.  ...  Donald Kossmann provided us with additional data for his dual-buffering system.  ... 
doi:10.1145/268998.266666 dblp:conf/sosp/CastroALM97 fatcat:l2dh4kz7wngpzkxonyn75zm64e

An interactive video delivery and caching system using video summarization

Sung-Ju Lee, Wei-Ying Ma, Bo Shen
2002 Computer Communications  
We also design a caching system that utilizes our video abstraction and summarization technique.  ...  We propose a novel scheme that provides users with the video summary (a number of key-frame images) before they download the file, and options for them to select the starting playback position.  ...  In this section, we propose a hybrid architecture where a master cache is used, but its role is reduced to only controlling the interactions and delivering the key-frames and prefixes.  ... 
doi:10.1016/s0140-3664(01)00414-5 fatcat:arkl6pkatjaznnyqj2bcq3gh2e

Object-oriented architectural support for a Java processor [chapter]

N. Vijaykrishnan, N. Ranganathan, R. Gadekarla
1998 Lecture Notes in Computer Science  
Also, three cache-based schemes: hybrid cache, hybrid polymorphic cache and two-level hybrid cache to implement virtual method invocations are presented.  ...  Java processors can be cost-effective to design and deploy in a wide range of embedded applications such as telephony and web tops.  ...  In Section 3, the instruction cache design for the Java processor is investigated.  ... 
doi:10.1007/bfb0054098 fatcat:7cyo4gvgdfdmpa2ssqvugtm4ie
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