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Predictable dynamic embedded data processing

Marc Geilen, Sander Stuijk, Twan Basten
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done.  ...  In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time  ...  It is based on the use of predictable, repeatable and composable platforms and exploits a run-time management approach to dynamically handle run-time use-cases.  ... 
doi:10.1109/samos.2012.6404194 dblp:conf/samos/GeilenSB12 fatcat:oskdckwjujexxhj5dyraehmuqa

Macroprogramming heterogeneous sensor networks using cosmos

Asad Awan, Suresh Jagannathan, Ananth Grama
2007 ACM SIGOPS Operating Systems Review  
COSMOS facilitates composition of complex real-world applications that are robust, scalable and adaptive in dynamic datadriven sensor network environments.  ...  An important and novel aspect of COSMOS is the ability to easily extend its component basis library to add rich macroprogramming abstractions to mPL, tailored to domain and resource constraints, without  ...  The key subsystems of the platform independent core include the scheduler, timer, dynamic memory manager, dynamic component loading and dataflow setup manager, dataflow API, device abstraction layer, and  ... 
doi:10.1145/1272998.1273014 fatcat:p7mhrmsauzbdjgr7hnasc3k7we

Macroprogramming heterogeneous sensor networks using cosmos

Asad Awan, Suresh Jagannathan, Ananth Grama
2007 Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007 - EuroSys '07  
COSMOS facilitates composition of complex real-world applications that are robust, scalable and adaptive in dynamic datadriven sensor network environments.  ...  An important and novel aspect of COSMOS is the ability to easily extend its component basis library to add rich macroprogramming abstractions to mPL, tailored to domain and resource constraints, without  ...  The key subsystems of the platform independent core include the scheduler, timer, dynamic memory manager, dynamic component loading and dataflow setup manager, dataflow API, device abstraction layer, and  ... 
doi:10.1145/1272996.1273014 dblp:conf/eurosys/AwanJG07 fatcat:wn653bjdlrem3gobfju4fiyyee

Design of embedded systems: formal models, validation, and synthesis

S. Edwards, L. Lavagno, E.A. Lee, A. Sangiovanni-Vincentelli
1997 Proceedings of the IEEE  
We review the variety of approaches to these problems that have been taken.  ...  This paper addresses the design of reactive real-time embedded systems.  ...  We also thank Harry Hsieh for his help with a first draft of this work.  ... 
doi:10.1109/5.558710 fatcat:4v34mhx7hjf5zjt4aap356zvb4

Design of Embedded Systems: Formal Models, Validation, and Synthesis [chapter]

Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli
2002 Readings in Hardware/Software Co-Design  
We review the variety of approaches to these problems that have been taken.  ...  This paper addresses the design of reactive real-time embedded systems.  ...  We also thank Harry Hsieh for his help with a first draft of this work.  ... 
doi:10.1016/b978-155860702-6/50009-0 fatcat:um7k7am5ergnrcizrrkbmzoz7a

Compiling Application-Specific Hardware [chapter]

Mihai Budiu, Seth Copen Goldstein
2002 Lecture Notes in Computer Science  
Our compiler exploits instruction level parallelism by using aggressive speculation and dynamic scheduling.  ...  The generated circuits use only localized computation structures; in consequence, we expect these circuits to be fast, to use little power and to scale well with program complexity.  ...  CCR-9876248 and by Darpa under contract #2156-CMU-ONR-0659. We are grateful to Tim Callahan for his comments on a preliminary version of this paper.  ... 
doi:10.1007/3-540-46117-5_88 fatcat:5djxytst4vgnjkc2lbp5sxylam

Models of computation and languages for embedded system design

A. Jantsch, I. Sander
2005 IEE Proceedings - Computers and digital Techniques  
Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment.  ...  The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs.  ...  The implementation purpose aims at providing a base and contract for the implementation and validation teams.  ... 
doi:10.1049/ip-cdt:20045098 fatcat:j6jhhgudbfatvcreknt4rwbkri

A Solution for Information Management in Logistics Operations of Modern Manufacturing Chains

Elisabeth Ilie-Zudor, Zsolt Kemény, Anikó Ekárt, Christopher D. Buckingham, László Monostori
2014 Procedia CIRP  
The paper will highlight aspects of information flows related to business process data visibility and observability in modern manufacturing networks.  ...  Often, instant and reliable decisions need to be taken based on huge, previously inconceivable amounts of heterogeneous, contradictory or incomplete data.  ...  time, users are provided with a verification tool to examine if the constructed dataflow network is consistent with regard to possible input/output types.  ... 
doi:10.1016/j.procir.2014.10.047 fatcat:rofycyz3vjepnaptghutnpm6o4

Heterogeneous models and analyses in the design of real-time embedded systems - an avionic case-study

Guillaume Brau, Nicolas Navet, Jérôme Hugues
2017 Proceedings of the 25th International Conference on Real-Time Networks and Systems - RTNS '17  
We then combine different real-time scheduling analyses so as to gradually define the task and network parameters and finally validate the schedulability of all activities of the system.  ...  In particular, we show that our approach makes it possible to combine heterogeneous models and analyses in the design of an avionic system.  ...  The verification of real-time contexts, applicability constraints or contracts can be seen as a kind of pre and/or post analysis.  ... 
doi:10.1145/3139258.3139281 dblp:conf/rtns/BrauNH17 fatcat:bug4faodkvaeldanvq3em77wzy

Worst-case throughput analysis of real-time dynamic streaming applications

Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
A challenge to dataflow-based design-time analysis of present-day streaming applications is their dynamic execution behavior.  ...  This thesis addresses this challenge with an automated approach that extracts a scenario-based analysis model for a class of parallel implementations, called Disciplined Dataflow Network (DDN).  ...  A dynamic dataflow modeling approach, based on SDFG scenarios and their FSM is referred to as FSM-based Scenario-aware Dataflow (FSM-SADF) [28, 89] , as defined in Definition 5.  ... 
doi:10.1145/2380445.2380517 dblp:conf/codes/SiyoumGMC12 fatcat:2vxjwmsjfvaf3dnfsm4k4dmwra

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 ACM SIGOPS Operating Systems Review  
This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures.  ...  from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33%  ...  CCR-9876248 and CCR-0205523 by DARPA under contracts MDA972-01-03-0005 and N000140110659 and by the SRC. The procedure inlining Suif pass was written by Tim Callahan.  ... 
doi:10.1145/1037949.1024396 fatcat:gycsxj3ebfhazpstc2dbx6ebiq

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 SIGARCH Computer Architecture News  
This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures.  ...  from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33%  ...  CCR-9876248 and CCR-0205523 by DARPA under contracts MDA972-01-03-0005 and N000140110659 and by the SRC. The procedure inlining Suif pass was written by Tim Callahan.  ... 
doi:10.1145/1037947.1024396 fatcat:5jkfjbhrdzamrdmhosahxd6dzu

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 SIGPLAN notices  
This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures.  ...  from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33%  ...  CCR-9876248 and CCR-0205523 by DARPA under contracts MDA972-01-03-0005 and N000140110659 and by the SRC. The procedure inlining Suif pass was written by Tim Callahan.  ... 
doi:10.1145/1037187.1024396 fatcat:5jeulzqygbfnnkch33wohm3imi

Spatial computation

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein
2004 Proceedings of the 11th international conference on Architectural support for programming languages and operating systems - ASPLOS-XI  
This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures.  ...  from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33%  ...  CCR-9876248 and CCR-0205523 by DARPA under contracts MDA972-01-03-0005 and N000140110659 and by the SRC. The procedure inlining Suif pass was written by Tim Callahan.  ... 
doi:10.1145/1024393.1024396 dblp:conf/asplos/BudiuVCG04 fatcat:ncnfj5flsrakpax7vhaf5io3ja

Synchronous Programming (Dagstuhl Seminar 13471)

Stephen A. Edwards, Alain Girault, Klaus Schneider, Marc Herbstritt
2014 Dagstuhl Reports  
For this reason, the synchronous composition is deterministic, which is a great advantage concerning predictability, verification of system design, and embedded code generation.  ...  techniques, software and hardware architectures, as well as extensions, transformations, and interfaces to other models of computations, in particular to asynchronous and hybrid systems.  ...  We briefly present a problem posed to use by Rafel Cases and Jordi Cortadella during a lunch organised by Gerard Berry. We propose solutions in the Simulink tool 3 and our language Zélus 4 .  ... 
doi:10.4230/dagrep.3.11.117 dblp:journals/dagstuhl-reports/EdwardsGS13 fatcat:b7aq6w2q4fawjjqtlfleujr3gi
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