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Dynamic hardware/software partitioning
2003
Proceedings of the 40th conference on Design automation - DAC '03
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We introduce a first approach to dynamic hardware/software partitioning. ...
We describe our system architecture and initial onchip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic ...
ACKNOWLEDGEMENTS This work was supported in part by the National Science Foundation, grants CCR-9876006 and CCR-0203829, by the Semiconductor Research Corporation, and by a Dept. of Education GAANN fellowship ...
doi:10.1145/775894.775896
fatcat:vqt6jeltpbdkrlmm7wuxxlyjq4
Dynamic hardware/software partitioning
2003
Proceedings of the 40th conference on Design automation - DAC '03
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We introduce a first approach to dynamic hardware/software partitioning. ...
We describe our system architecture and initial onchip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic ...
ACKNOWLEDGEMENTS This work was supported in part by the National Science Foundation, grants CCR-9876006 and CCR-0203829, by the Semiconductor Research Corporation, and by a Dept. of Education GAANN fellowship ...
doi:10.1145/775832.775896
dblp:conf/dac/StittLV03
fatcat:gxuxvphsuzcn7j3xspmjcrt4eu
Hardware/software partitioning of software binaries
2002
Computer-Aided Design (ICCAD), IEEE International Conference on
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Although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. ...
We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned ...
We thank Jason Villarreal for developing the loop analysis tools. ...
doi:10.1145/774572.774596
dblp:conf/iccad/StittV02
fatcat:nqm4xfwshbdqjpc55unanl72cy
On the hardware-software partitioning problem
2003
ACM Transactions on Design Automation of Electronic Systems
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The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). ...
It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. ...
Grajal for his help in the formulation of the cost function. ...
doi:10.1145/785411.785412
fatcat:xbbma6lllbhy3lgrppxdvcy7m4
Hardware/software partitioning of software binaries
2005
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05
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We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source ...
The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. ...
The source code for the H.264 decoder was provided by Freescale Semiconductor. ...
doi:10.1145/1084834.1084905
dblp:conf/codes/StittVME05
fatcat:auo4il5m2ffjbpn4kt6mdwyhaa
Analyzing communication overheads during hardware/software partitioning
2003
Microelectronics Journal
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With this methodology we have optimised the design-space exploration of a partitioning tool, achieving up to a 2.5 performance speed-up, while increasing the time needed to perform the partitioning by ...
Current partitioning codesign tools often simplify the communication channel features by working with generic abstract channels, which in a following step, are mapped into the actual ones. ...
This problem is referred in literature as Hardware/Software (HW/SW) partitioning. ...
doi:10.1016/s0026-2692(03)00168-x
fatcat:57hk3f3k4bcw7g37g7syv36sbe
A configurable logic architecture for dynamic hardware/software partitioning
Proceedings Design, Automation and Test in Europe Conference and Exhibition
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We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. ...
Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software ...
logic architecture
(WCLA) for dynamic hardware/software partitioning. ...
doi:10.1109/date.2004.1268892
dblp:conf/date/LyseckyV04
fatcat:n3b6srdjmnb37gss7yfwpnraga
A performance-oriented hardware/software partitioning for datapath applications
2008
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08
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This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. ...
The mapping process is generalized in order to allow an automatic exploration of the solution space, that identifies the best performance/area configurations among several application-architecture combinations ...
Argy Krikelis and the European Technology Center of Altera (UK) for providing support and the technology for the methodology evaluation. ...
doi:10.1145/1450135.1450149
dblp:conf/codes/FrigerioS08
fatcat:zb7nw32n4jha5gpedz33lyrmim
A dynamically constrained genetic algorithm for hardware-software partitioning
2006
Proceedings of the 8th annual conference on Genetic and evolutionary computation - GECCO '06
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The partitioning obtained can then be used to build the different functional units of a processor well suited for a large customization, thanks to its architecture that uses only one instruction, Move ...
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. ...
This is the case when GAs are applied to the partitioning problem, which is one of the tasks required for the hardware-software codesign of embedded systems. ...
doi:10.1145/1143997.1144134
dblp:conf/gecco/MudryZT06
fatcat:az4gmz5m6jcjppoorrjr5duwky
Profiling tools for hardware/software partitioning of embedded applications
2003
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems - LCTES '03
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Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. ...
We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning ...
Figure 3 shows a target architecture that could benefit by mapping loops to hardware. One might observe that no additional delay is required to fetch the data for the configurable logic fabric. ...
doi:10.1145/780732.780759
dblp:conf/lctrts/SureshNVVS03
fatcat:v4p2dh3w4je5vfboetbmr2iwlu
Profiling tools for hardware/software partitioning of embedded applications
2003
SIGPLAN notices
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The file type is application/pdf.
Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. ...
We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning ...
Figure 3 shows a target architecture that could benefit by mapping loops to hardware. One might observe that no additional delay is required to fetch the data for the configurable logic fabric. ...
doi:10.1145/780731.780759
fatcat:kcwibnuntjhedmg3bvqoot7ame
Profiling tools for hardware/software partitioning of embedded applications
2003
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems - LCTES '03
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The file type is application/pdf.
Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. ...
We also study the potential speedup that can be achieved using a configurable system on a chip, consisting of a CPU embedded on an FPGA, as an example application of these tools in hardware/software partitioning ...
Figure 3 shows a target architecture that could benefit by mapping loops to hardware. One might observe that no additional delay is required to fetch the data for the configurable logic fabric. ...
doi:10.1145/780757.780759
fatcat:cbwhklkmdjdb5dutlqh5fgmgmi
Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning
2008
International journal of parallel programming
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Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an ...
parallel execution of the partitioned software and hardware. ...
Binary-level partitioning opens the door to dynamic hardware/software partitioning, in which an executing binary is dynamically optimized by moving software kernels to on-chip configurable logic. ...
doi:10.1007/s10766-008-0079-0
fatcat:4rdl72vxzrfuxhkjthyy6sveu4
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
2007
International Journal of Applied Mathematics and Computer Science
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Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning In recent years, several heuristics have been proposed for the hardware/software partitioning problem. ...
The aim of this paper is to systematically evaluate the possibilities of applying the Kernighan-Lin heuristic to hardware/software partitioning. ...
Work on Hardware/Software Partitioning. Hardware/software partitioning is a central task in hardware/software co-design (Wolf, 2003) . ...
doi:10.2478/v10006-007-0022-3
fatcat:eii2rlplqnd65drseq7izooale
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits
2008
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08
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In this paper, we present a hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations ...
While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing ...
Figure 2 : 2 Hardware/software partitioning methodology for floating point applications. ...
doi:10.1145/1450135.1450148
dblp:conf/codes/SaldanhaL08
fatcat:zaup7skeyregzkpkhywuyyce2i
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