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Artificial neural networks in hardware: A survey of two decades of progress

Janardan Misra, Indranil Saha
2010 Neurocomputing  
Parallel digital implementations employing bit-slice, systolic, and SIMD architectures, implementations for associative neural memories, and RAM based implementations are also outlined.  ...  We outline underlying design approaches for mapping an ANN model onto a compact, reliable, and energy efficient hardware entailing computation and communication and survey a wide range of illustrative  ...  Based upon the purpose of reconfiguration (prototyping and simulation, density enhancement, and topology adaptation) as well as data representation techniques (integer, floating point, and bit stream arithmetic  ... 
doi:10.1016/j.neucom.2010.03.021 fatcat:regzu6sshvekzd5wxcuaiytgqu

VLIW Processor Architectures and Algorithm Mappings for DSP Applications [chapter]

Ravi Managuli, Yongmin Kim
2001 Signal Processing and Communications  
All the partitioned operations can be executed only on the Integer floating point and arithmetic graphics unit (IFGALU) while ALU supports load/ store and branch operations as discussed in Section III.E  ...  Each cluster has 64 32-bit general registers, 16 predicate registers, a pair of 128-bit registers, an Integer Arithmetic Logic Unit (IALU) and an Integer Floating-point Graphics Arithmetic Logic Unit (  ... 
doi:10.1201/9780203908068.ch2 fatcat:lmmvpoutjff3vjoebay77njbxq

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  The material will vary by topic but in general most volumes will include fundamental material (when appropriate), methods, designs and techniques. More information about this series at  ...  It was a tremendous help to see to possibilities of FDSOI in silicon very early on.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques [chapter]

Ivan Ratković, Nikola Bežanić, Osman S. Ünsal, Adrian Cristal, Veljko Milutinović
2015 Advances in Computers  
Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years.  ...  Both computer architects and circuit designers intent to reduce power and energy (without a performance Advances in Computers, Volume 98 # 2015 Elsevier Inc.  ...  [22, 24] where they divide the processor into five domains: Front end, Integer, Floating point, Load/Store, and External (Main Memory) which interfaces via queues.  ... 
doi:10.1016/bs.adcom.2015.04.001 fatcat:5voowf7sizcpxaumb74nelc25a

0 Instruction Set Architecture [chapter]

2003 Digital Design and Computer Organization  
For example, the PICO VLIW processor template (shown in Figure 2 .6) uses a single register file for each data-type (integer, floating point, etc.), this severely limits the number of operations which  ...  The constructed processor is a wide VLIW ASIP with 4 16-way vector issue-slots, 2 vector memories for storing the input and output buffers, 3 scalar issue-slots (including fifo and control operations),  ...  De, in dit proefschrift voorgestelde methoden, richten zich dan ook vooral op verbeteringen in zowel de ontwerp evaluatie als de verdere automatisering van de ontwerp kandidaat selectie.  ... 
doi:10.1201/b12403-15 fatcat:mygaz2meibgljew5tzvmuw6x5i

The history of the microprocessor

Michael R. Betker, John S. Fernando, Shaun P. Whalen
2002 Bell Labs technical journal  
BHT -Branch history table FP -Floating point int/fp -Integer/floating point ROP -RISC opcode by using insulators with lower dielectric constants.  ...  A family of products using readonly memory (ROM)-programmable variations of the basic calculator design was in view.  ... 
doi:10.1002/bltj.2082 fatcat:w2ilifumlzeotdhnncopefkxkm

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Kunle Olukotun, Lance Hammond, James Laudon
2007 Synthesis Lectures on Computer Architecture  
From the wide set of Java benchmarks, thread parallelism could be exploited from integer, floating-point, and multimedia benchmarks.  ...  Eqntott was parallelized manually by modifying a single bit vector comparison routine that is responsible for 90% of the execution time of the application [5] .  ...  As was mentioned previously, in a very large loop body a single memory dependence violation near the end of the loop can result in a large amount of work being discarded.  ... 
doi:10.2200/s00093ed1v01y200707cac003 fatcat:qyjilavdhfcmlnc46l5sxg7ssq

A lifetime optimal algorithm for speculative PRE

Jingling Xue, Qiong Cai
2006 ACM Transactions on Architecture and Code Optimization (TACO)  
In addition to being computationally optimal in the sense that the total number of dynamic computations for an expression in the transformed code is minimized, MC-PRE is also lifetime optimal since the  ...  The key in achieving lifetime optimality lies not only in finding a unique minimum cut on a transformed graph of a given CFG, but also in performing a data-flow analysis directly on the CFG to avoid making  ...  ACKNOWLEDGMENTS We wish to thank the reviewers and editors for their helpful comments and suggestions. This work is partially supported by an ARC grant DP0452623.  ... 
doi:10.1145/1138035.1138036 fatcat:6jxnqgxw6vbzpoefpqlt56pacm

Reconfigurable architecture for real-time image compression on-board satellites

Kristian Manthey, David Krutz, Ben Juurlink
2015 Journal of Applied Remote Sensing  
A Xilinx Virtex-5QV enables thereby compressing images with a width of up to 4096 pixels without the use of external memory.  ...  It operates at a clock frequency of 100 MHz and processes two image pixels per clock cycle.  ...  It is a PhD program about the investigation of the civil security technologies in Germany, which had started in August 2010.  ... 
doi:10.1117/1.jrs.9.097497 fatcat:32vnqdyok5dzxp2vv5oocpmwjq

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet
2014 2014 9th International Design and Test Symposium (IDT)  
ADC Analog to Digital Converter AFM Atomic Force Microscopy ALU Arithmetic and Logic Unit ASIC Application Specific Integration Circuit Ath Adder Depth, the maximum number of serial adder-operations from  ...  The biggest challenge is to ensure satisfactory control performances with a minimal hardware.  ...  ., − = ∈ as well as rational numbers of the form f a x 2 / = ("binary" rational), I a ∈ , and f is a positive integer. • Floating-point number format: This is the most common approach.  ... 
doi:10.1109/idt.2014.7038608 dblp:conf/idt/OudjidaLBC14 fatcat:ykr7hhrd7ndy5jbmu53hb3t7vm

A Vhdl Course For Electronics Engineering Technology

Robert W. Nowlin, Rajeswari Sundararajan
1997 Annual Conference Proceedings   unpublished
The Electronics and Computer Engineering Technology Department at Arizona State University has offered a course in VHDL to both undergraduate and graduate students for the past three years.  ...  An attractive serendipity of a course in VHDL is that students are forced to learn (or re-learn) more accurately how hardware elements operate because they can cannot model the hardware operation unless  ...  The use of VHDL and VERILOG in producing designs speeds their completion and insures a higher quality product.  ... 
doi:10.18260/1-2--6893 fatcat:o52kmwnznbdvhflvnyogorup4q

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems

R. Bertran, Y. Sugawara, H. M. Jacobson, A. Buyuktosunoglu, P. Bose
2013 IBM Journal of Research and Development  
Accurate energy accounting for shared virtualized environments using pmc-based power modeling techniques. In .  ...  Energy accounting for shared virtualized environments under dvfs using pmc-based power models.  ...  In addition, we gratefully acknowledge Robert Walkup and John Gunnels for their help with the benchmarks.  ... 
doi:10.1147/jrd.2012.2227580 fatcat:e2yb6krghzdvfkaavxy7ha3li4

Application of FPGAs in acceleration of numerical solution of differential equations

Watany Ben Jamil, Université D'Ottawa / University Of Ottawa, Université D'Ottawa / University Of Ottawa
This thesis proposes a new application for Field Programmable Gate Array in the acceleration of the numerical solution of differential equations.  ...  This thesis demonstrates that using a computational platform with hardware-enabled accelerator can speed up the task of computing high-order derivatives by at least one-order-of-magnitude.  ...  Emad Gad for their guidance and support. To My wife for the time she spent reading this document.To Dr. Mohammed Mohammed for his help in Latex  ... 
doi:10.20381/ruor-19327 fatcat:jgrnkifgyfb6vdwnsecm35reg4

GPU power modeling and architectural enhancements for GPU energy efficiency [article]

Jan Lucas, Technische Universität Berlin, Technische Universität Berlin, Ben Juurlink
Initially designed for 3D graphics, they evolved into general purpose accelerators, able to outperform CPUs on many tasks. The architecture of GPUs is optimized for massively parallel applications.  ...  This reduces the required control logic but also results in lower performance in applications with irregular control flow.  ...  execution resources for integer, floating point, and memory instructions.  ... 
doi:10.14279/depositonce-7874 fatcat:wbmij23r2ngtfaskosnrsxt5gu

Simulating cardiac dynamics using Maxeler dataflow super-computing

Lilly Maria Treml, Ezio Bartocci, Haris Isakovi
This technology relies on dataflow paradigm, in which the data processing elements, called pipelines, operate concurrently and are connected in a way that the output of one element is the input for the  ...  In the last decade, there has been a great effort to accelerate computer-based cardiac simulation by implementing efficient parallel algorithms that leverage multi-cores CPU and many-cores GPUs currently  ...  The standard types for numerics used in computation (integer, floating point, etc.) are offered by the MaxCompiler as DFEVars.  ... 
doi:10.34726/hss.2018.41907 fatcat:4xkcwbdp5rcudo7oiusdrzq2mm
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