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Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor

Emmanuel Touloupis, James A. Flint, Member, Vassilios A. Chouliaras, David D. Ward
2007 IEEE transactions on computers  
., UK and the Department of Electronic and Electrical Engineering of Loughborough University, United Kingdom.  ...  In Section 3, the fault injection technique used in this study is presented and, in Section 4, the results of the fault injection campaign are discussed in detail.  ...  In many cases, fault injection experiments have been used for demonstrating the efficiency in error rate prediction of a fault injection platform or method.  ... 
doi:10.1109/tc.2007.70766 fatcat:yahhg5j54rg2hhru2y2v6wfsu4

Online diagnosis of hard faults in microprocessors

Fred A. Bower, Daniel J. Sorin, Sule Ozev
2007 ACM Transactions on Architecture and Code Optimization (TACO)  
A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault.  ...  We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy.  ...  ACKNOWLEDGMENTS We thank Alvy Lebeck and the rest of the Duke Architecture Reading Group for helpful feedback on this paper.  ... 
doi:10.1145/1250727.1250728 fatcat:lq2g3lffebaatixrm7rmycqdbe

RedThreads: An Interface for Application-level Fault Detection/Correction through Adaptive Redundant Multithreading [article]

Saurabh Hukerikar, Keita Teranishi, Pedro C. Diniz, Robert F. Lucas
2017 arXiv   pre-print
In the presence of accelerated fault rates, which are projected to be the norm on future exascale systems, it will become increasingly difficult for high-performance computing (HPC) applications to accomplish  ...  The redundant multithreading (RMT) approach offers lightweight replicated execution streams of program instructions within the context of a single application process.  ...  For the higher fault injection rates, the spread among the execution times is higher since the experiments cover a range of fault patterns.  ... 
arXiv:1610.01728v2 fatcat:cufj74obybfqlnlnbut26klram

Memory-span concepts and the synthesis of sequential machines in feedback shift-register form

Robert L. Martin
1967 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)  
Checkpointing Fault Detection in Cryptographic Systems Overview of Ciphers; Security Attacks through Fault Injection; Countermeasures. 26 Case Studies Non-Stop Systems; Stratus Systems; Cassini  ...  Limits in ILP: Introduction; Studies of the limitations of ILP; Limitations on ILP for realizable processors; 16 Memory Data Flow Architecture: Data Flow and Hybrid architecture; Case study: VLIW architecture  ...  FAULT-TOLERANT SYSTEMS Mobile Application languages -XML, Java, J2ME and JavaCard Introduction, XML, JAVA, Java 2 Micro Edition (J2ME), JavaCard.  ... 
doi:10.1109/focs.1967.19 dblp:conf/focs/Martin67 fatcat:fwn5xjv7mbcsja5xrhcmdo6ipe

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

A. Moshovos, G.S. Sohi
2001 Proceedings of the IEEE  
Weaving the "raw" semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture.  ...  behavior.  ...  Empirical studies of program behavior show that many instructions tend to produce the same value every time they execute.  ... 
doi:10.1109/5.964438 fatcat:ewlfjz4cyzgdfbrw54ubn4pfu4

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Yi Ma, Hongliang Gao, M. Dimitrov, Huiyang Zhou
2015 IEEE Transactions on Parallel and Distributed Systems  
In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor.  ...  In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery.  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their insightful and valuable comments.  ... 
doi:10.1109/tpds.2007.1080 fatcat:zuuuxuazcrdqloaawnvirnnk4m

Leveraging the Openness and Modularity of RISC-V in Space

Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone
2019 Journal of Aerospace Information Systems  
This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture.  ...  of fault tolerance and technology readiness level.  ...  Acknowledgments This work was supported by the European Space Agency under the NPI Program, Cobham Gaisler AB, and Delft University of Technology.  ... 
doi:10.2514/1.i010735 fatcat:b4ckmbr2uvhvzi57ltesqyiokm

A defect-tolerant accelerator for emerging high-performance applications

Olivier Temam
2012 SIGARCH Computer Architecture News  
Most fault models are abstract and cannot demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators.  ...  for heterogeneous multi-cores may become a major micro-architecture research issue.  ...  Acknowledgments We would like to thank the anonymous reviewers for their helpful comments and advices.  ... 
doi:10.1145/2366231.2337200 fatcat:xblg6iwi7ze6pe7bylgh5dvzwe

Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery

Yi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou
2007 IEEE Transactions on Parallel and Distributed Systems  
In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor.  ...  In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery.  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their insightful and valuable comments.  ... 
doi:10.1109/tpds.2007.4288106 fatcat:rww3jiwbgnebpizagla44fedya

A defect-tolerant accelerator for emerging high-performance applications

Olivier Temam
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
Most fault models are abstract and cannot demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators.  ...  for heterogeneous multi-cores may become a major micro-architecture research issue.  ...  Acknowledgments We would like to thank the anonymous reviewers for their helpful comments and advices.  ... 
doi:10.1109/isca.2012.6237031 dblp:conf/isca/Temam12 fatcat:uvkqsyuxozbftn5udee6wjoaqi

Relax

Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam
2010 Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10  
The combination of emerging applications and emerging many-core architectures makes software recovery a viable alternative to hardware-based fault recovery.  ...  Software recovery can harness these properties in ways that hardware recovery cannot. We describe Relax, an architectural framework for software recovery of hardware faults.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers and the Vertical group for comments and the Wisconsin Condor project and UW CSL for their assistance.  ... 
doi:10.1145/1815961.1816026 dblp:conf/isca/KruijfNS10 fatcat:swqxe67uvvavdpas7a5vce63je

Relax

Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam
2010 SIGARCH Computer Architecture News  
The combination of emerging applications and emerging many-core architectures makes software recovery a viable alternative to hardware-based fault recovery.  ...  Software recovery can harness these properties in ways that hardware recovery cannot. We describe Relax, an architectural framework for software recovery of hardware faults.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers and the Vertical group for comments and the Wisconsin Condor project and UW CSL for their assistance.  ... 
doi:10.1145/1816038.1816026 fatcat:3mvyjijsbbac3dq3nypez7xfz4

Approaches to Software Based Fault Tolerance - A Review

Goutam Kumar Saha
2005 Computer Science Journal of Moldova  
The aim of this paper is to cover past and present approaches to software implemented fault tolerance that rely on both software design diversity and on single but enhanced design.  ...  This paper presents a review work on various approaches to software based fault tolerance.  ...  [117] have proposed a transient fault tolerant design that takes good advantage of the resource for parallel executions found in a superscalar processor.  ... 
doaj:372c628d0d4148ec8297ac09a277140d fatcat:flvj2teivvfmzn7wfb2fw7rwl4

Fingerprinting

Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk
2004 Proceedings of the 11th international conference on Architectural support for programming languages and operating systems - ASPLOS-XI  
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010.  ...  This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection.  ...  Mak, Shubu Mukherjee, and the anonymous reviewers for their valuable feedback on early drafts of this paper.  ... 
doi:10.1145/1024393.1024420 dblp:conf/asplos/SmolensGKFHN04 fatcat:yp6lbocm7jcondwkxqx6wr3t3q

Fingerprinting

Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk
2004 SIGARCH Computer Architecture News  
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010.  ...  This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection.  ...  Mak, Shubu Mukherjee, and the anonymous reviewers for their valuable feedback on early drafts of this paper.  ... 
doi:10.1145/1037947.1024420 fatcat:fokczd32qrg3posw6ftcin362m
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