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A clock-gating method for low-power LSI design

T. Kitahara, F. Minami, T. Ueda, K. Usami, S. Nishio, M. Murakata, T. Mitsuhashi
Proceedings of 1998 Asia and South Pacific Design Automation Conference  
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly.  ...  We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit.  ...  Acknowledgment The authors would like to thank T.Matoba, Y.Maki, A.Fujimoto and H.Muraoka for providing the practical design data used for the experiment.  ... 
doi:10.1109/aspdac.1998.669476 dblp:conf/aspdac/KitaharaMUUNMM98 fatcat:3ctdf7daczcb7hncrqxieu52lm

Power-supply circuits for ultralow-power subthreshold MOS-LSIs

Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006 IEICE Electronics Express  
A low-voltage power supply circuit is developed for micropower CMOS LSI applications, especially for microwatt smart-sensor LSIs.  ...  The switched converter lowers battery voltage 1.5-3 V to a low voltage of 0.5-0.7 V to drive the series regulator, and the series regulator provides LSI logic gates with a power voltage of 0.4-0.6 V such  ...  For subthreshold-operated LSIs, we developed a power-supply circuit consisting of a low-voltage DC-DC converter and a series regulator specialized for microwatt operation.  ... 
doi:10.1587/elex.3.464 fatcat:oulgaqzwlbdrhojwdtd4sgw3ty

Power analysis techniques for SoC with improved wiring models

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information  ...  The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.  ...  In this research, we take the approach of designing wire load models exclusively for the clock nets and reduce the errors in the power estimate for the clock lines to less than one tenth of previous methods  ... 
doi:10.1145/566408.566476 dblp:conf/islped/SakamotoYMMHY02 fatcat:qhmnqr7mlrdwnh5wykxeduq3ja

Power analysis techniques for SoC with improved wiring models

T. Sakamoto, T. Yamada, M. Mukuno, Y. Matsushita, Y. Harada, H. Yasuura
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information  ...  The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.  ...  In this research, we take the approach of designing wire load models exclusively for the clock nets and reduce the errors in the power estimate for the clock lines to less than one tenth of previous methods  ... 
doi:10.1109/lpe.2002.146750 fatcat:affl7jcjhfaxra5zh2uc5omusu

Power analysis techniques for SoC with improved wiring models

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets (2) The use of layout information  ...  The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.  ...  In this research, we take the approach of designing wire load models exclusively for the clock nets and reduce the errors in the power estimate for the clock lines to less than one tenth of previous methods  ... 
doi:10.1145/566475.566476 fatcat:6323nfzeyfatzbtx7w23cpkbcm

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor

T. SEKI
2005 IEICE transactions on electronics  
High-performance and low-power microprocessors are key to PDA applications.  ...  In this paper, a dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM.  ...  Hagiwara for help, suggestions, and support.  ... 
doi:10.1093/ietele/e88-c.4.520 fatcat:4zj36rq45jblpjjvn3balgdcti

Dynamic voltage and frequency management for a low-power embedded microprocessor

M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, M. Shimura
2005 IEEE Journal of Solid-State Circuits  
High-performance and low-power microprocessors are key to PDA applications.  ...  In this paper, a dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM.  ...  Hagiwara for help, suggestions, and support.  ... 
doi:10.1109/jssc.2004.838021 fatcat:ksvix526mrggfogl35y37ufoei

Power Supply Circuits for Ultralow-Power Subthreshold CMOS Smart Sensor LSIs

Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006 2006 International Symposium on Intelligent Signal Processing and Communications  
A low-voltage power supply circuit was developed for micropower CMOS LSI applications, with microwatt smartsensor LSIs being the specific focus.  ...  The switched converter lowers battery voltage by 1.5-3 V to a low voltage of 0.5-0.7 V that drives the series regulator, and the series regulator provides LSI logic gates with a power voltage of 0.4-0.6  ...  This paper describes a design method for an efficient microwatt DC-DC converter with control circuits for subthreshold LSI applications. Figure 2 shows the SC voltage divider.  ... 
doi:10.1109/ispacs.2006.364719 fatcat:rcpderow3ralrewpijvs35fwlm

An Effective Overlap Removable Objective for Analytical Placement

Syota KUWABARA, Yukihide KOHIRA, Yasuhiro TAKASHIMA
2013 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
General-synchronous framework is expected to obtain LSI circuits with high performance and low power consumption.  ...  Low-distortion and wideband techniques were devised for RF lownoise amplifiers and mixers. Yukihide Kohira: We investigate design automation methodology for LSI circuits.  ...  trated on circuit design of low-power HP-CQMODs and linear power amplifiers in the transmitter, and have started research on frequencyshift filtering methods.  ... 
doi:10.1587/transfun.e96.a.1348 fatcat:jszihuroefej5d3lagkjun5pru

Basic concepts of timing-oriented design automation for high-performance mainframe computers

Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
This paper outlines the concepts and the key technologies for designing high-performance mainframe computers.  ...  We perceive that both of the goals must be achieved for the timely development of mainframe computers that meet the market demand.  ...  The result was a reduction of clock skew to one third for an ECL LSI with 12,000 gates compared with the results obtained without the new methods.  ... 
doi:10.1145/127601.127663 dblp:conf/dac/TeraiGWKEHH91 fatcat:6rv4sx5wwzdufh56kuchypjylu

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions

Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010 IPSJ Transactions on System LSI Design Methodology  
This paper proposes a low-power ASIP generation method by automatically extracting minimum execution conditions of pipeline registers for clock gating.  ...  For highly effective power reduction by clock gating, it is important to create minimum execution conditions, which can shut off redundant clock supplies for registers.  ...  Acknowledgments This work is supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with Synopsys Corporation.  ... 
doi:10.2197/ipsjtsldm.3.222 fatcat:cnacnuqosfbshn447emvzq5nkq

A novel clock generation scheme for globally asynchronous locally synchronous systems

Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
2005 Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05  
This paper focuses on a clock generation scheme for implementation of GALS circuits on commercial FPGAs which are mostly synchronous.  ...  In addition, general design considerations to successfully implement a GALS circuit on FPGAs are discussed. At the end we present a GALS Reed-Solomon decoder as a practical example.  ...  INTRODUCTION The new SoC designs face the challenge of distributing a high-speed low-skew clock in a large die.  ... 
doi:10.1145/1057661.1057733 dblp:conf/glvlsi/SalehNNPS05 fatcat:kadqezoztjg6rpkodt6yi23k7a

The impact of ASIC devices on the SEU vulnerability of space-borne computers

R. Koga, W.R. Crain, K.B. Crawford, S.J. Hansel, S.D. Pinkerton, T.K. Tsubota
1992 IEEE Transactions on Nuclear Science  
Penzin for their generou°F PGAs, they also tend to be a bit more difficult to program. assistance. Thanks are also due M. Sarpa and K.A.  ...  OwyanL Because of this, a preliminary step might be to replace SSI and (Actel), W.C. Schneider and A.F. Yee (LSI), R.L. Woodruff MSI component circuits with FPGAs. If further reductions in and PJ.  ...  For this tievice the inverters while the clock pulse is "low."  ... 
doi:10.1109/23.211354 fatcat:t3zh3gunkbahjp3wbzxtu4i7ma

Stretchable EMI Measurement Sheet With 8 $\times$ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18$\ \mu$m Silicon CMOS LSIs for Electric and Magnetic Field Detection

Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2010 IEEE Journal of Solid-State Circuits  
The sheet consists of an 8 8 coil array, a 2 V organic CMOS row decoder and a column selector, 40% stretchable interconnects with carbon nanotubes, and 0.18 m silicon CMOS circuits for electric and magnetic  ...  The sheet detects the total power of an electric field in the band up to 700 MHz and that of a magnetic field up to 1 GHz.  ...  ., Ltd. for fruitful discussions.  ... 
doi:10.1109/jssc.2009.2034446 fatcat:uialkpudvvfajdsyhf2p5kvddu

In-Situ Supply-Noise Measurement in LSIs with Millivolt Accuracy and Nanosecond-Order Time Resolution [chapter]

Yusuke Kanno
2011 Applications of Digital Signal Processing  
Morino of Renesas Electronics Corporation for their valuable advice and assistance.  ...  Ishibashi of The University of Electro-Communications, for their support and helpful comments. We also express our gratitude to Y. Tsuchihashi, G. Tanaka, Y. Miyairi, T. Ajioka, and N.  ...  This technology trend can also be applied to low-cost and low-power LSIs designed especially for mobile use.  ... 
doi:10.5772/27833 fatcat:pisoj36nefhjvaka3s6ovwguaa
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