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Neural Network Architecture for Hybrid Network-On-Chip using Scalable Spiking for Man Machine Interface

S. Santhosh Kumar, S. Vidhya, M. M. Shanmugapriya
2017 Indian Journal of Science and Technology  
In this research Spiking neural networks (SNNs) arrange to emulate scientific discipline within the class brain supported neurons parallel arrays that communicate through spike events.  ...  The scalability of the adopted H-NoC approach under completely different situations is shown by analytical results show, while synthesis and simulation analysis reveal, area of low-cost, and delay for  ...  Conclusion The writers have designed a novel gradable intelligence agent plan that allows cluster of neurons to be imposed on hardware exploitation a gradable array of intelligence agent routers.  ... 
doi:10.17485/ijst/2017/v10i16/113492 fatcat:v5oflzwl4vbshjj43l27korvh4

A fast multicast IP-routing lookup scheme

Keng-Ming Huang, Chung-Ju Chang
2003 IEEE Communications Letters  
This letter proposes a fast multicast IP-routing lookup scheme, which adopts a compression bit map conception for forwarding information.  ...  ACKNOWLEDGMENT The authors thank the anonymous reviewers for their comments to improve the presentation of the paper.  ...  The existence of the membership for these (group, source) pairs can be represented by the cross points of a grid.  ... 
doi:10.1109/lcomm.2003.809988 fatcat:rlsi32odb5gttmke2icpntfzv4

General hardware multicasting for fine-grained message-passing architectures

Matthew Naylor, Simon W. Moore, David Thomas, Jonathan R. Beaumont, Shane Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew Brown
2021 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)  
However, in the absence of cache coherency, there can be a lack of hardware support for one-to-many communication patterns, which are prevalent in some application domains.  ...  distributed hardware multicasting, implemented on top of a many-  ...  One of the strengths of cache-coherent architectures is hardware support for one-to-many communication patterns.  ... 
doi:10.1109/pdp52278.2021.00028 fatcat:sb2fafsaifdvjhqi3pkfjadnae

AN ASSESSMENT OF THE CONNECTION MACHINE

ROBERT SCHREIBER
1993 International journal of high speed computing  
The CM-2 is an example of a connection machine. The strengths and problems of this implementation are considered.  ...  Then important issues in the architecture and programming environment of connection machines in general are considered.  ...  A better hardware grid may be the answer for some applications, but a faster router should have the top priority.  ... 
doi:10.1142/s0129053393000220 fatcat:simo6to2hnamhec4itephqirvm

A New Approach for Distributed Computing in Embedded Systems

Sergey Salibekyan, Peter Panfilov
2015 Procedia Engineering  
In this paper, we introduce a new computational model, known as OAA (Object-Attribute Architecture) and present the general characteristics of an OA-methodology to support the design and simulation of  ...  However, the trend in embedded systems design in recent years has been towards highly distributed architectures with support for concurrency, data and control flow, and scalable distributed computations  ...  Acknowledgements This work was partly funded by the project "Research of architectures of distributed dataflow computer systems for the semantic analysis of natural language".  ... 
doi:10.1016/j.proeng.2015.01.457 fatcat:kheyptco7vceri7nunqvg4jwwi

Hardware accelerated convolutional neural networks for synthetic vision systems

Clement Farabet, Berin Martini, Polina Akselrod, Selcuk Talay, Yann LeCun, Eugenio Culurciello
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
In this paper we present a scalable hardware architecture to implement large-scale convolutional neural networks and state-of-the-art multi-layered artificial vision systems.  ...  We present a performance comparison between a software, FPGA and ASIC implementation that shows a speed up in custom hardware implementations.  ...  The ALUs are independent processing tiles laid out on a two-dimensional grid. Each tile is composed of: a Global Router, Local Routers, a Streaming Operator.  ... 
doi:10.1109/iscas.2010.5537908 dblp:conf/iscas/FarabetMATLC10 fatcat:h56kpgpkebdctgmr74eroq4734

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems

Michel Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola Celanovic, Srinivas Devadas
2011 2011 IEEE 32nd Real-Time Systems Symposium  
This approach yields real-time execution on the order of 1μs simulation time step (including input/output latency) for a broad class of power electronics converters.  ...  We present the hardware architecture, and describe the process of power electronic circuit compilation.  ...  One of the key underlying physical layers of the smart grid is power electronics. Power electronics is a class of cyber-physical systems.  ... 
doi:10.1109/rtss.2011.35 dblp:conf/rtss/KinsyKCMCD11 fatcat:p5g4mwqlcbgpvovedevvjpqtyq

Zooming in on Network-on-Chip Architectures [chapter]

Israel Cidon
2010 Lecture Notes in Computer Science  
We present a new classification of chip architectures into three categories with different requirements from their NoCs.  ...  The aim of this paper is to expose the networking community to the concept of network-on-chip (NoC), an emerging field of study within the VLSI realm, in which networking principles play a significant  ...  ACKNOWLEDGMENTS The authors thank Evgeny Bolotin, Roman Gindin, Ran Ginosar, Zvika Guz, Avinoam Kolodny, Ehud Shavit, and Isask'har Walter for helpful discussions and for many of the initial results presented  ... 
doi:10.1007/978-3-642-11476-2_1 fatcat:gsipffo6v5covck6jqsk2jeimy

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications [article]

Marcelo Orenes Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi
2022 arXiv   pre-print
Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing  ...  data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; (4) novel traffic-aware task scheduling hardware that maintains  ...  architecture connected by a NoC optimized for irregular communication (headerless task-routing based on the index of the array they access). • A hardware unit (TSU) that removes task-invocation overheads  ... 
arXiv:2207.13219v2 fatcat:7adzjehlkzfqtkyloqx7v3p2cm

NoC-Based FPGA: Architecture and Routing

Roman Gindin, Israel Cidon, Idit Keidar
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs).  ...  We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes.  ...  DyNoC [14] is an architecture for adaptive routing using reconfigurable hardware.  ... 
doi:10.1109/nocs.2007.31 dblp:conf/nocs/GindinCK07 fatcat:aa4xlta62jbstdjo6tdtuibcxy

Scalable hardware monitors to protect network processors from data plane attacks

Kekai Hu, Harikrishnan Chandrikakutty, Russell Tessier, Tilman Wolf
2013 2013 IEEE Conference on Communications and Network Security (CNS)  
In this paper, we present the design of a Scalable Hardware Monitoring Grid, which allows the dynamic sharing of hardware monitoring resources among processor cores.  ...  One possible defense mechanism for these resourceconstrained network processors is the use of hardware monitoring systems that track the operations of each processor core.  ...  Thus, our Scalable Hardware Monitoring Grid provides an effective and efficient mechanism for defending network infrastructure from a new class of attacks. VIII.  ... 
doi:10.1109/cns.2013.6682721 dblp:conf/cns/HuCTW13 fatcat:wsfgq4pnb5akjmkvu7lzcr6gd4

Adventures with a Reconfigurable Research Platform

John Wawrzynek
2007 2007 International Conference on Field Programmable Logic and Applications  
Arrays of Soft Processors on FPGAs  RAMP hardware development activity centered at BWRC.  NSF grant for staff.  ...  Router design Compile to FPGA Parallel languages RAMP RAMP RAMP Provides High Visibility for FPGAs  Today, FPGAs get used in undergraduate hardware courses and by a few graduate research efforts  ... 
doi:10.1109/fpl.2007.4380615 dblp:conf/fpl/Wawrzynek07 fatcat:6uiskuucjzfjlgipjcwcez5alm

SIP-enabled Optical Burst Switching architectures and protocols for application-aware optical networks

Georgios Zervas, Yixuan Qin, Reza Nejabati, Dimitra Simeonidou, Franco Callegati, Aldo Campi, Walter Cerroni
2008 Computer Networks  
Furthermore, various SIP over OBS layering architectures, utilizing a number of end-to-end resource discovery protocols (both for network and nonnetwork (IT) resources) are presented and analyzed.  ...  This paper presents a novel application-aware network architecture for emerging IT services and future Internet applications.  ...  ., Grid user, e-Science) sends a request to the SIP proxy of the ingress edge router to the OBS cloud.  ... 
doi:10.1016/j.comnet.2008.02.016 fatcat:ne6gwrk4prbinjikrwpe7aydru

A hexagonal array machine for multilayer wire routing

R. Venkateswaran, P. Maxumder
1990 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A technique for measuring the performance of a hardware accelerator, in terms of the average delay incurred over a full-grid machine, is suggested.  ...  A hexagonal machine of dimension C G , with about 3kC processors, can handle a k-layer grid consisting of kC' grid points at about the same speed as a full-grid machine with kG' processors.  ...  Shin, Director of the Real-Time Computing Laboratory for his stimulating discussions about the hexagonal mesh with wraparound topology.  ... 
doi:10.1109/43.62734 fatcat:oziwp2kttbcbzj3kubano5rjem

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism.  ...  To adapt to small and large-grain concurrency, the TRIPS architecture contains four out-of-order, 16-wide-issue Grid Processor cores, which can be partitioned when easily extractable fine-grained parallelism  ...  Acknowledgments We thank the anonymous reviewers for their suggestions that helped improve the quality of this paper.  ... 
doi:10.1145/859618.859667 fatcat:w2yv6e2ixjhmrjc2sigtq7ms2y
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