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Model and analysis for combined package and on-chip power grid simulation

Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
2000 Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00  
We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power distribution grids.  ...  These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a statistical switching current model for the switching devices.  ...  To ensure the robust operation of a processor, the impact of above effects on the power grid voltage must be analyzed.  ... 
doi:10.1145/344166.344574 dblp:conf/islped/PandaBCZYR00 fatcat:pzowx2luxvfsle5xru63brb724

Model and analysis for combined package and on-chip power grid simulation

R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, R. Ramaraju
2000 ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)  
We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power distribution grids.  ...  These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a statistical switching current model for the switching devices.  ...  To ensure the robust operation of a processor, the impact of above effects on the power grid voltage must be analyzed.  ... 
doi:10.1109/lpe.2000.155274 fatcat:twfmbbl2s5cnrny7xtknpaptfe

Parallel domain decomposition for simulation of large-scale power grids

Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen
2007 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids.  ...  Results for circuits with more than four million nodes indicate that parallel DD with LU factorization is most suitable for power grid simulation.  ...  Background The power grid of an integrated circuit is traditionally described as a large-scale linear system. Simulation of power grids usually consists of both DC and transient analysis.  ... 
doi:10.1109/iccad.2007.4397243 dblp:conf/iccad/SunZMS07 fatcat:itxopbbxrjf25eude6jlvqkphm

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks

Sanjay Pant, David Blaauw
2006 Computer Design (ICCD '99), IEEE International Conference on  
The placement of on-die decoupling capacitors (decap) between the power and ground supply grids has become a common practice in high performance processor designs.  ...  In this paper, we present a new active decap circuit that significantly increase the effectiveness of decap in suppressing power supply fluctuations.  ...  Acknowledgements Authors are thankful to Ravikishore Gandikota and Visvesh Sathe for helpful discussions.  ... 
doi:10.1109/iccd.2006.4380811 dblp:conf/iccd/PantB06 fatcat:bgvuiehxeffhtl3qt4xylipaxe

3D power distribution network co-design for nanoscale stacked silicon ICs

Amirali Shayan, Xiang Hu, He Peng, Mikhail Popovich, Wanping Zhang, Chung-Kuan Cheng, Lew Chua-Eoan, Xiaoming Chen
2008 2008 IEEE-EPEP Electrical Performance of Electronic Packaging  
In this paper, we propose an efficient flow for the analysis and co-design of large 3D power distribution networks (3D PDN).  ...  In the established 3D PDN model, we incorporate the on-chip voltage regulator module (VRM) and effect of on-chip inductance.  ...  The transient simulation result at one time point depends on the results from previous time points. Thus, it will take a long time to simulate large networks.  ... 
doi:10.1109/epep.2008.4675863 fatcat:kaupqh7yyzhxde6owbeduxrwzu

Power delivery system architecture for many-tier 3D systems

Michael B. Healy, Sung Kyu Lim
2010 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)  
In this work we explore power delivery system design for these large scale devices. We have developed a scalable many-tier design that contains one tier of processors and eight tiers of DRAM.  ...  First, we examine the addition of a dynamic noise-limiting turn-on policy and show that it can reduce dynamic power supply noise by 37% with almost no impact on system performance.  ...  Acknowledgments The authors acknowledge the support of the Interconnect Focus Center (IFC), one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation  ... 
doi:10.1109/ectc.2010.5490753 fatcat:mckm7r62wfhlbjuqbgvfnyrvhy

Interconnect and noise immunity design for the Pentium 4 processor

Rajesh Kumar
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Finally,our test chip results and use of a distributed power grid to manage inductance is described.  ...  This paper describes the key challenges, design methods, CAD and learnings in the area of interconnect and noise immunity design for the Intel Pentium 4 processor.  ...  Paul Madland for guidance and for having a feel for where the silicon problems would really be and our management for sticking with our fullchip wire/noise direction, even though at the time, it looked  ... 
doi:10.1145/775832.776068 dblp:conf/dac/Kumar03 fatcat:sgcj3xpoezg3tcvn54m2fpzega

Applications of one-cycle control to improve the interconnection of a solid oxide fuel cell and electric power system with a dynamic load

Allie E. Auld, Fabian Mueller, Keyue Ma Smedley, Scott Samuelsen, Jack Brouwer
2008 Journal of Power Sources  
The load data are combined with the following models that are designed to account for physical features: a One-Cycle Control grid-connected inverter, a One-Cycle Control active power filter, an SOFC, and  ...  Adding distributed generation (DG) is a desirable strategy for providing highly efficient and environmentally benign services for electric power, heating, and cooling.  ...  V a , V b , and V c are the grid voltages at the point of contact, and i a , i b , and i c are the incoming grid currents. The power stage circuit and large-signal model are shown in Fig. 4 .  ... 
doi:10.1016/j.jpowsour.2007.12.072 fatcat:n5fva2ehmrcanesdcbgkbedoay

Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices

Borislav Alexandrov, Owen Sullivan, William J. Song, Sudhakar Yalamanchili, Satish Kumar, Saibal Mukhopadhyay
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The simulation results show potential for extending the time for which a chip and package can sustain a high power load.  ...  Using thermal compact models of the chip and package with integrated TECs, the control principles for TEC-assisted transient cooling are presented.  ...  The coanalysis shows that TEC-assisted transient cooling allows a processor to sustain a high-power pulse for a longer period without violation of the thermal threshold.  ... 
doi:10.1109/tvlsi.2013.2278951 fatcat:4d5aftv5ivekho6u5g44cfpz3e

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Muhammad Abrar Akram, In-Chul Hwang, Sohmyung Ha
2021 IEEE Access  
First, when a large-load-current transient occurs anywhere in the power grid, the load current does not flow from the most adjacent LDO only but also from other neighboring LDOs to quickly mitigate the  ...  Then, O(s) can be approximated as a first-order system, the loop is stable. 1) Transient-boost Control To enhance the load transient response and reduce the voltage undershoot (∆ V REG ) for load current  ... 
doi:10.1109/access.2021.3067644 fatcat:prbru7pojvcs3mxildfwce36rq

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 SIGARCH Computer Architecture News  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  network (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike.  ...  Clearly, both pad count and pad locations have a large effect on on-chip voltage noise. Other researchers have studied the effect of C4 optimization during pre-RTL design. For example, Wang et al.  ... 
doi:10.1145/2678373.2665728 fatcat:kkwbrdtdrjasfetcshx643vr3e

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  network (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike.  ...  Clearly, both pad count and pad locations have a large effect on on-chip voltage noise. Other researchers have studied the effect of C4 optimization during pre-RTL design. For example, Wang et al.  ... 
doi:10.1109/isca.2014.6853199 dblp:conf/isca/ZhangWMSS14 fatcat:yruivsyndbapvmp4izc3sbsc34

Thermal and Power Delivery Challenges in 3D ICs [chapter]

Pulkit Jain, Pingqiang Zhou, Chris H. Kim, Sachin S. Sapatnekar
2009 Integrated Circuits and Systems  
Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery.  ...  Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint.  ...  Of all these techniques, the decaps are arguably the most powerful method for reducing transient noise.  ... 
doi:10.1007/978-1-4419-0784-4_3 fatcat:7fa5tugnajdcfgamzuroore4xm

Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures

Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
cost or encroaching on bumps sites needed for I/O.  ...  As a result, the targeted system MTTF can be achieved with significantly reduced power bump count (e.g., 43% less) and a small extra noise margin (e.g., 0.5% Vdd IR drop).  ...  Once a power supply bump fails, the PDN's effective impedance as observed by nearby circuit will increase, because now the supply current has to come from neighbouring power bumps through the lateral on-chip  ... 
doi:10.1109/tvlsi.2015.2501353 fatcat:7kbo75bzt5ga7mijg5jcmx2l7u

Real time implementation of STATCOM to analyze transient and dynamic characteristics of wind farm

Adnan Sattar, Ahmed Al-Durra, S.M. Muyeen
2011 IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society  
Wind turbines and generators of a wind farm, power grid, and control system are realized in the large time-step main network.  ...  In this paper, a grid connected wind farm with a static synchronous compensator (STATCOM) is modeled in Real Time Digital Simulator (RTDS) environment to analyze its dynamic and transient characteristics  ...  ACKNOWLEDGEMENT The authors would like to acknowledge "Electric Machine Laboratory" of KITIMI INSTITUTE OF TECHNOLOGY, JAPAN for giving the permission to use the wind speed data in this work.  ... 
doi:10.1109/iecon.2011.6119918 fatcat:ztb67nnoxrgllpz376n3fmuhdm
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