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A CASE FOR HYBRID INSTRUCTION ENCODING FOR REDUCING CODE SIZE IN EMBEDDED SYSTEM-ON-CHIPS BASED ON RISC PROCESSOR CORES

Bakthavatsalam
2014 Journal of Computer Science  
In the study, we propose a variation of Hybrid Instruction Encoding (HIE) for the embedded processors.  ...  Considering the large market share of embedded systems, it is worth investing in a new architecture and development of dedicated HIE-RISC processor cores for portable embedded systems based on SoCs.  ...  Our paper proposes replacing the 'uniform instruction size' feature by 'hybrid instruction size' in the embedded RISC cores used in BOPES so as to reduce the code memory space, for embedded programs.  ... 
doi:10.3844/jcssp.2014.411.422 fatcat:lc5etkqml5ebpkoxdtwhxzopfa

Code Size Reduction in Embedded Systems with Redesigned ISA for RISC Processors

Govindarajalu B, K. M. Mehata
2013 International Journal of Computer Applications  
Reducing the size of a program is a major goal in modern embedded systems. Large code occupies more space in the Chip and also causes higher power consumption because of increased memory traffic.  ...  Analysis of RISC object code for Embedded Applications, using an offline tool developed by the authors, establishes the scope for a new class of processor exclusively for embedded applications.  ...  V.P.Ramamurthi, Chairman, Dhanalakshmi College of Engineering for extending the research facilities, and Mrs. Shyamala Dharmar, CEO, Vael's Academy, for her suggestions towards effective presentation.  ... 
doi:10.5120/10690-5594 fatcat:kjleqjsnbbdyfgssp3wdjezfni

DSP architectures

Edwin J. Tan, Wendi B. Heinzelman
2003 SIGARCH Computer Architecture News  
In this paper, w e will explain t h e various D S P architectures and its silicon i m p l e m e n t a t i o n .  ...  A b s t r a c t -A s far as t h e future of c o m m u n i c ations is concerned, w e have s e e n that there is great d e m a n d for audio and v i d e o data to c o m p l e m e n t t e x t .  ...  Stephen McAleavey for his time and effort in directing the authors to relevant sources of DSP material and for his insights into the subject. [13] [14]  ... 
doi:10.1145/882105.882108 fatcat:mswoipgie5e37bfyb54qniz3di

A Survey on RISC-V Security: Hardware and Architecture [article]

Tao Lu
2021 arXiv   pre-print
Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA).  ...  In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices  ...  The integration test of their XMSS accelerator and embedded RISC-V processor shows that the hash-based post-quantum signature can be actually used in a variety of embedded applications.  ... 
arXiv:2107.04175v1 fatcat:hr6avyprj5dvpav2pvnmfmvg2a

A design space exploration framework for reduced bit-width instruction set architecture (rISA) design

Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt, Alex Nicolau
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
Code size is a critical concern in many embedded system applications, especially those using RISC cores.  ...  One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, spaceefficient (usually  ...  The authors would like to thank all the EXPRESSION team members for their valuable support in this framework.  ... 
doi:10.1145/581199.581228 fatcat:faaogatajbbfvcj362erfghnn4

A design space exploration framework for reduced bit-width instruction set architecture (rISA) design

Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt, Alex Nicolau
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
Code size is a critical concern in many embedded system applications, especially those using RISC cores.  ...  One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, spaceefficient (usually  ...  The authors would like to thank all the EXPRESSION team members for their valuable support in this framework.  ... 
doi:10.1145/581227.581228 fatcat:xunqyb64grfjtjstx6yvcpmwge

Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing [chapter]

Paul Graham, Brent Nelson
1999 Lecture Notes in Computer Science  
For high-performance, embedded digital signal processing, digital signal processors (DSPs) are very important.  ...  In this paper, we discuss how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip.  ...  One hybrid processor-RL system called Pleiades [9, 10] has specifically targeted ultra-low power, embedded digital signal processing.  ... 
doi:10.1007/978-3-540-48302-1_1 fatcat:gh6lczuuifcedmixpebairjy4i

Hardware Support for Embedded Java [chapter]

Martin Schoeberl
2011 Distributed, Embedded and Real-time Java Systems  
However, Azul Systems has included a read barrier in their RISC based chip-multiprocessor system [11] .  ...  The interface between the RISC processor and the Java processor is based on cross-core interrupts.  ... 
doi:10.1007/978-1-4419-8158-5_7 fatcat:jnk6dqak3bg67jmyflimvw3i24

Energy-Efficient System-Level Design [chapter]

Luca Benini, Giovanni De Micheli
2002 Power Aware Design Methodologies  
and communication channel as well as system and application software onto a single chip.  ...  Moving from a set of case studies, we give an overview of energy-efficient systemlevel design, emphasizing a component-based approach.  ...  Each of the major signal processing cores contains a 16-bit RISC processor and dedicated hardware accelerators. The system is a three-way asymmetric on-chip multiprocessor.  ... 
doi:10.1007/0-306-48139-1_16 fatcat:rikxlmoqmjfd3o3whfmbnvymwm

Adaptation of DSP Processors for 3G and 4G Wireless Communication
English

VINNI SHARMA, TANUJA KASHYAP
2014 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
Qualcomm Snapdragon Processors Snapdragon is a family of mobile system on a chip (SoC) processor architecture provided by Qualcomm.  ...  The sequencing mechanism in VLIW depends on an instruction format. In VLIW, all operation latencies in a particular implementation are fully open to software.  ...  CSoC's are modified for a specific application. Its architecture consists of processor core, memory, ASIC cores, and on-chip reconfigurable hardware units.  ... 
doi:10.15662/ijareeie.2014.0307041 fatcat:2xgq7v2aczfufhsizdju2llqsi

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Simon Rokicki, Erven Rohou, Steven Derrien
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In order to provide dynamic adaptation of the performance/energy trade-off, systems today rely on heterogeneous multi-core architectures (different micro-architectures on a chip).  ...  In this paper we present Hybrid-DBT, an open-source, hardware accelerated DBT system targeting VLIW cores.  ...  DISCUSSION In this work, we have developed from scratch a complete hardware/software co-designed system for executing RISC-V binaries on a VLIW processor.  ... 
doi:10.1109/tcad.2018.2864288 fatcat:a2axpoyilrajlmxujmtwwxll7q

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.  ...  This paper proposes a new architecture for a singlechip MPEG-2 video encoder with scalability for HDTV and demonstrates its exibility and usefulness.  ...  Ryota Kasai of the NTT System Electronics Laboratories for supporting this work. Thanks are also due to the members of the NTT Visual Communication Laboratory for their helpful suggestions.  ... 
doi:10.1145/307418.307445 fatcat:nosqizpxprbizdqhvftfuuymmm

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Muhammad Yasir Qadri, Hemal S. Gujarathi, Klaus D. McDonald-Maier
2009 Journal of Computers  
This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip.  ...  Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors.  ...  ACKNOWLEDGMENT This research is in part supported by the UK Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/C005686/1, EP/C014790/1 and EP/C54630X/1.  ... 
doi:10.4304/jcp.4.10.927-942 fatcat:nau6udvp4vd3ffon3zbwmzsgje

A novel network processor for security applications in high-speed data networks

Kyriakos G. Vlachos
2003 Bell Labs technical journal  
The PRO3 incorporates an innovative scheme-a reduced instruction set computing (RISC)-based pipelined module with line-rate throughput-that makes it possible to process high-and low-level streaming operations  ...  Using microcode profiling and simulation, we give performance results for a stateful-inspection firewall application with network address translation (NAT) support.  ...  A system based on a highly programmable reduced instruction set computing (RISC) core can provide flexibility, but it sacrifices speed to programmability.  ... 
doi:10.1002/bltj.10058 fatcat:y635livrurahxhedyfqc47hhke

A large-area integrated multiprocessor system for video applications

M. Rudack, M. Redeker, J. Hilgenstock, S. Moch, J. Castagne
2002 IEEE Design & Test of Computers  
Consequently, the systems consist of a signifi-6 This 16.89-cm 2 multiprocessor system performs coding of high-resolution video streams in real time.  ...  In addition, such systems need dynamic RAM (DRAM) for image frame storage, a memory controller, and video interfaces adapted to the image sensors.  ...  We thank our colleagues Dieter Treytnar, Ole Mende, and Hendrik Reissmann for their contributions.  ... 
doi:10.1109/54.980049 fatcat:vlbkbi7esnehtgcnp4df4qzvae
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