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Dual-access way-prediction cache for embedded systems

Yul Chu, Jin Hwan Park
<span title="2014-05-20">2014</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qdjkc7427rgarmzaexozmec3eq" style="color: black;">EURASIP Journal on Embedded Systems</a> </i> &nbsp;
In this paper, we propose an enhanced way-prediction cache, dual-access way-prediction (DAWP) cache, to cope with the weakness of the WP cache.  ...  Way-prediction (WP) caches have advantages of reducing power consumption and latency for highly associative data caches and thus are favorable for embedded systems.  ...  In this case, the latency and power dissipation are based on the accesses to the index table and the predicted bank, i.e., analogous to the operation on the direct-mapped cache. (2) The second case is  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1186/1687-3963-2014-16">doi:10.1186/1687-3963-2014-16</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/tmakjv3o2ndaffh45cphuoxwwm">fatcat:tmakjv3o2ndaffh45cphuoxwwm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20140617135401/http://jes.eurasipjournals.com:80/content/pdf/1687-3963-2014-16.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/91/13/91131b4c992e210a6156a2870fda623c8b7c70d5.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1186/1687-3963-2014-16"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> springer.com </button> </a>

A media cache structure for multimedia applications in embedded systems

Jung-hoon Lee
<span title="">2011</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
The proposed cache consists of three parts, i.e., a dual direct mapped cache, a fully associative spatial buffer, and a dynamic fetch unit.  ...  When a cache miss occurs, the dynamic fetch controller generates fetch signals for one of three block sizes (e.g., 64-byte, 128-byte, or 192-byte) depending on information that is kept on recent block  ...  dual direct mapped cache organization.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.8.1302">doi:10.1587/elex.8.1302</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/tzogvhrq3ffivjpsy5oix3sfpu">fatcat:tzogvhrq3ffivjpsy5oix3sfpu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181102011235/https://www.jstage.jst.go.jp/article/elex/8/16/8_16_1302/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c6/45/c645078e68063ae8bd554c347572101a8fb3e385.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.8.1302"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Tradeoffs in two-level on-chip caching

N. P. Jouppi, S. J. E. Wilton
<span title="1994-04-01">1994</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/35q3ync5nbhnjfpylznlz57lyi" style="color: black;">SIGARCH Computer Architecture News</a> </i> &nbsp;
Abstract The performance of two-level on-chip caching is investigated for a range of technology and architecture assumptions. The area and access time of each level of cache is modeled in detail.  ...  The results indicate that for most workloads, twolevel cache configurations (with a set-associative second level) perform marginally better than single-level cache configurations that require the same  ...  We would also like to thank Joel Emer and Bob Nix for their very helpful comments on a recent draft of this paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/192007.192015">doi:10.1145/192007.192015</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/aebvttqphjhtpfuylphzqh774a">fatcat:aebvttqphjhtpfuylphzqh774a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810083145/http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-93-3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2e/4b/2e4b33b429afdc74320ceae139ec5182947ad4fe.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/192007.192015"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Author retrospective for the dual data cache

Antonio González, Carlos Aliagas
<span title="">2014</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3sq4a52jknfqpfyjfszyrlkedm" style="color: black;">25th Anniversary International Conference on Supercomputing Anniversary Volume -</a> </i> &nbsp;
tuned for a different type of locality.  ...  In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each  ...  The TOC (Temporal Cache) is a direct-mapped cache with a block size of 8 bytes and the SOC (Spatial Cache) is a four-way associative cache with a block size of 32 bytes.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2591635.2591652">doi:10.1145/2591635.2591652</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ics/GonzalezA14.html">dblp:conf/ics/GonzalezA14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jcn7vf4ad5ft3doknh7lksah6u">fatcat:jcn7vf4ad5ft3doknh7lksah6u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706124707/http://upcommons.upc.edu/bitstream/handle/2117/26675/p32-gonzalez.pdf%3Bjsessionid%3D1CCBB5638DA71B9A6AD066FD3BFD2183?sequence%3D1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/65/59/6559bd7c865b05b02658a1077062b773a289b529.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2591635.2591652"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A data cache with multiple caching strategies tuned to different types of locality

Antonio González, Carlos Aliagas, Mateo Valero
<span title="">1995</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3sq4a52jknfqpfyjfszyrlkedm" style="color: black;">Proceedings of the 9th international conference on Supercomputing - ICS &#39;95</a> </i> &nbsp;
tuned for a different type of locality.  ...  In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each  ...  The TOC (Temporal Cache) is a direct-mapped cache with a block size of 8 bytes and the SOC (Spatial Cache) is a four-way associative cache with a block size of 32 bytes.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224538.224622">doi:10.1145/224538.224622</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ics/GonzalezAV95.html">dblp:conf/ics/GonzalezAV95</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uecbhpniavbhhbviwwv3g277om">fatcat:uecbhpniavbhhbviwwv3g277om</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706124707/http://upcommons.upc.edu/bitstream/handle/2117/26675/p32-gonzalez.pdf%3Bjsessionid%3D1CCBB5638DA71B9A6AD066FD3BFD2183?sequence%3D1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/65/59/6559bd7c865b05b02658a1077062b773a289b529.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/224538.224622"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A data cache with multiple caching strategies tuned to different types of locality

Antonio González, Carlos Aliagas, Mateo Valero
<span title="">2014</span> <i title="ACM Press"> 25th Anniversary International Conference on Supercomputing Anniversary Volume - </i> &nbsp;
tuned for a different type of locality.  ...  In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each  ...  The TOC (Temporal Cache) is a direct-mapped cache with a block size of 8 bytes and the SOC (Spatial Cache) is a four-way associative cache with a block size of 32 bytes.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2591635.2667170">doi:10.1145/2591635.2667170</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/keac3k5sizg3hpt3qxmiwrnx7i">fatcat:keac3k5sizg3hpt3qxmiwrnx7i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706124707/http://upcommons.upc.edu/bitstream/handle/2117/26675/p32-gonzalez.pdf%3Bjsessionid%3D1CCBB5638DA71B9A6AD066FD3BFD2183?sequence%3D1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/65/59/6559bd7c865b05b02658a1077062b773a289b529.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2591635.2667170"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Virtual-address caches.2. Multiprocessor issues

M. Cekleov, M. Dubois
<span title="">1997</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
For example, when all physical addresses map into the same superset in the dual directory, the effective cache size is reduced to the size of one superset in the dual directory.  ...  Since there is no time to search through the superset for synonyms upon receiving a bus request, hardware solutions must rely on a reverse cache map.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.641599">doi:10.1109/40.641599</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/aiqvivczfjcxbc46vvup5ap4qa">fatcat:aiqvivczfjcxbc46vvup5ap4qa</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830021747/http://liacs.leidenuniv.nl/~csca/ca2014/cekleov.97.2.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/04/f004c564a3e70d76220e3739e4cad3ddb4ef7a77.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.641599"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Dual-cache Structure Based Large Scale Texture Mapping for Real-time Terrain Rendering

Dong Tian, Xiaodong Wang, Xin Zheng
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/po2jyf5dznbr7drljinouf5hdq" style="color: black;">2008 IEEE Conference on Robotics, Automation and Mechatronics</a> </i> &nbsp;
time dual-cache structure based updating method, which effectively reduces the frequency of data refresh.  ...  There are two key problems in efficient large scale texture mapping for terrain rendering-efficient data organization and real time data updating in memory.  ...  For this problem, we propose a dual-cache structure.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ramech.2008.4681477">doi:10.1109/ramech.2008.4681477</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ram/TianWZ08.html">dblp:conf/ram/TianWZ08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lrapuzdy3zap7foqzkqhqvvu5m">fatcat:lrapuzdy3zap7foqzkqhqvvu5m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813042425/http://vigir.missouri.edu/~gdesouza/Research/Conference_CDs/IEEE_CyberIntSys_2008/PDFFILES/Papers/P1020.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1d/0f/1d0ffbe5c678f6bc88f4c22de5248e4ae57f8847.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ramech.2008.4681477"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Jongsok Choi, Kevin Nam, Andrew Canis, Jason Anderson, Stephen Brown, Tomasz Czajkowski
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hss6rlelz5by5nc6dnosoj2luu" style="color: black;">2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines</a> </i> &nbsp;
on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines).  ...  Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speedup swings from 0.73× to 6.14×,  ...  For each cache and line size, we lastly investigate direct-mapped (one-way) caches vs. 2-way setassociative caches.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fccm.2012.13">doi:10.1109/fccm.2012.13</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fccm/ChoiNCABC12.html">dblp:conf/fccm/ChoiNCABC12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uvxy4z2bx5cedjav4adqahapuq">fatcat:uvxy4z2bx5cedjav4adqahapuq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20160928232134/http://www.eecg.toronto.edu:80/~choijon5/pubs/james_fccm.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/59/e6/59e67d0fadad931a0d51ad7df3456dff0babf9e6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/fccm.2012.13"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Static Timing Analysis of Shared Caches for Multicore Processors

Wei Zhang, Jun Yan
<span title="2012-12-30">2012</span> <i title="Korean Institute of Information Scientists and Engineers"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/xvozmuuqprbr3mvk4th3ep6pea" style="color: black;">Journal of Computing Science and Engineering</a> </i> &nbsp;
Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared  ...  This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform.  ...  we have 2 threads (i.e., T 1 and T 2 ) running on a dual-core with a shared 2-way set-associative cache.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5626/jcse.2012.6.4.267">doi:10.5626/jcse.2012.6.4.267</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cd66etfpjvaahp67fucc5ozqs4">fatcat:cd66etfpjvaahp67fucc5ozqs4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808053538/http://central.oak.go.kr/repository/journal/11751/E1EIKI_2012_v6n4_267.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/eb/22/eb22a7c7594f6426cdaf5aa4327b1c801181db8d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5626/jcse.2012.6.4.267"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches [chapter]

Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
<span title="">2007</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
This approach yields an overall performance improvement of 24.7% over the best fixed-size caches for dual-thread workloads, and 19.2% for single-threaded applications.  ...  Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications.  ...  Overall, a 24.7% improvement is realized for dual-thread workloads by implementing adaptive cache organizations and an MCD design style within an SMT processor.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-69338-3_10">doi:10.1007/978-3-540-69338-3_10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uxasiybaafh6hc7nagvh4n6nwq">fatcat:uxasiybaafh6hc7nagvh4n6nwq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100623172829/http://www.csl.cornell.edu/%7Ealbonesi/research/papers/hipeac07.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/03/64/0364d8e4b327ba648c651505202ef404ae86caf1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-540-69338-3_10"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches

Michel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger, Andreas Moshovos
<span title="">2013</span> <i title="IEEE Conference Publications"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2013</a> </i> &nbsp;
This work proposes a dual grain filter which successfully predicts whether an access is a hit or a miss in most cases.  ...  Experimental results with commercial and scientific workloads show that a 158KB dual-grain filter can correctly predict data block residency for 85% of all accesses to a 256MB DRAM cache.  ...  Therefore using a DRAMC in the same way as a conventional on-die cache may result in a considerable latency and energy increase for some memory accesses.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.7873/date.2013.032">doi:10.7873/date.2013.032</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/El-NacouziAPZJM13.html">dblp:conf/date/El-NacouziAPZJM13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xtg4oahxp5d6dc2mnhhwuw6nny">fatcat:xtg4oahxp5d6dc2mnhhwuw6nny</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20140913075112/http://www.eecg.toronto.edu:80/~enright/elnacouzi-date13.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/aa/74/aa74370a8ec81a95bcdf714584834f78c2d1d75c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.7873/date.2013.032"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Power estimation for architectural exploration of HW/SW communication on system-level buses

William Fornaciari, Donatella Sciuto, Christina Silvano
<span title="">1999</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/h4zelo33ojdfzbwajaf5qlthey" style="color: black;">Proceedings of the seventh international workshop on Hardware/software codesign - CODES &#39;99</a> </i> &nbsp;
The paper aims at providing a framework for architectural exploration of a system design, focusing on the power consumption estimation of memory communication.  ...  Experimental results, conducted on bus streams generated by a real microprocessor and a stream generator, show how the variation of cache parameters and the introduction of bus encoding at the different  ...  First, for the same cache size, the miss rate is reduced when passing from direct mapped to two-and four-way, while it is constant or slightly increases from four-way to eight-way.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/301177.301516">doi:10.1145/301177.301516</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/codes/FornaciariSS99.html">dblp:conf/codes/FornaciariSS99</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ldx53jxomjeqhguy5a3urxvh24">fatcat:ldx53jxomjeqhguy5a3urxvh24</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923032944/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1999/codes99/pdffiles/6_3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/fe/ed/feedb6199347116f49a934f94a11b9face50da8d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/301177.301516"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling

Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi
<span title="">2012</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells  ...  VTD-Cache allows for a significant reduction in power consumption while addressing reliability issues raised by memory cell process variability.  ...  Way and cache figure are obtained for a case study, for a 32 kB four-way associative cache organizations.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2011.2106523">doi:10.1109/tvlsi.2011.2106523</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4hxmg3mgezerlehfqoudpq55xq">fatcat:4hxmg3mgezerlehfqoudpq55xq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20130918230545/http://ece.gmu.edu:80/~hhomayou/files/VTD.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/83/22/832208fdd116646d473cd6cfe039373f8ed16949.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2011.2106523"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Virtual-address caches. Part 1: problems and solutions in uniprocessors

M. Cekleov, M. Dubois
<span title="">1997</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
For example, the maximum size for a direct-mapped cache is the size of one page.  ...  Thus, researchers have proposed many ways to find synonyms fast, independently of the cache size. They all rely on a reverse map indexed with physical addresses.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.621215">doi:10.1109/40.621215</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uaztemiztbgqdmmja34qd5jnca">fatcat:uaztemiztbgqdmmja34qd5jnca</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829120535/http://www.ece.umd.edu/courses/enee646.F2007/Cekleov1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/46/a4/46a41eb7c59a70e5ee46694183a0d38923b317f3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.621215"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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