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A Case for Deconstructing Hardware Transactional Memory Systems

Mark D. Hill, Derek Hower, Kevin E. Moore, Michael M. Swift, Haris Volos, David A. Wood, Albert Cohen, María J. Garzarán, Christian Lengauer, Samuel P. Midkiff
2008
Our thesis is that deconstructing transactional memory into separate, interchangeable components facilitates TM adoption in two ways.  ...  Major hardware and software vendors are curious about transactional memory (TM), but are understandably cautious about committing to hardware changes.  ...  Deconstruction is also useful for constructing hybrid TM systems, where software and hardware cooperatively provide transactions.  ... 
doi:10.4230/dagsemproc.07361.3 fatcat:blr32nzu2ngv7ljspocpdlqp2q

From ARIES to MARS

Joel Coburn, Trevor Bunker, Meir Schwarz, Rajesh Gupta, Steven Swanson
2013 Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles - SOSP '13  
We use EAWs to build MARS, a WAL scheme that provides the same as features ARIES [26] (a widely-used WAL system for databases) but avoids making disk-centric implementation decisions.  ...  We have implemented EAWs and MARS in a nextgeneration SSD to demonstrate that the overhead of EAWs is minimal compared to normal writes, and that they provide large speedups for transactional updates to  ...  This work is supported by NSF Award 1219125 and by hardware donations from Xilinx.  ... 
doi:10.1145/2517349.2522724 dblp:conf/sosp/CoburnBSGS13 fatcat:ub6xqs5zmvee3bxvjp24p7q33y

Distributed Computing Column 58

Jennifer L. Welch
2015 ACM SIGACT News  
Most of all, my thanks and admiration to Maurice Herlihy for his seminal contributions, not only to transactional memory, but to nonblocking algorithms, topological analysis, and so many other aspects  ...  References Concluding Thoughts While the discussion above spans much of the history of transactional memory, and mentions many open questions, the coverage has of necessity been spotty, and the choice  ...  As with transactional memory systems, transactions against NV-RAM would provide a mechanism for composing operations across multiple data structures [10] .  ... 
doi:10.1145/2789149.2789163 fatcat:ueub5knoofar3jee6plc763yni

Monitoring Data Structures Using Hardware Transactional Memory [chapter]

Shakeel Butt, Vinod Ganapathy, Arati Baliga, Mihai Christodorescu
2012 Lecture Notes in Computer Science  
TxInt leverages concurrency control mechanisms implemented in harware transactional memory (HTM) systems to additionally enforce programmer-specified consistency properties on data structures at runtime  ...  In this paper, we present the design and implementation of TxInt, a system to detect data structure corruptions.  ...  Researchers have also made the case for deconstructing HTM systems, and reusing HTM hardware for applications beyond concurrency control [26, 19] . In particular, the position paper Hill et al.  ... 
doi:10.1007/978-3-642-29860-8_26 fatcat:d3kmjoc4pbbu5ax7fkbcuywrgy

Deconstructing Voice-over-IP

JIE LI, PENG-FEI CAO, XU-QING JIA
2019 DEStech Transactions on Engineering and Technology Research  
Our focus in this paper is not on whether the well-known knowledge-based algorithm for the emulation of checksums by Herbert Simon runs in _(n) time, but rather on exploring a semantic tool for harnessing  ...  Such a hypothesis might seem perverse but is derived from known results.  ...  Acknowledgement Project Supported by Education Department Foundation of Jiangsu Province (17KJD520007), Key Program for Modern Educational Technology in Jiangsu Province(2017-R-59068),Virtual Simulation  ... 
doi:10.12783/dtetr/icicr2019/30597 fatcat:zhhyqf4ijff57dju2mpaqbbqdi

Transactional Memory, 2nd edition

Tim Harris, James Larus, Ravi Rajwar
2010 Synthesis Lectures on Computer Architecture  
This allows using hardware for the common case and software for the exceptional case.  ...  BASIC TRANSACTIONAL MEMORY Chapter 2 introduces TM, sketches its use, and presents a broad taxonomy of design choices for software and hardware TM systems.  ...  He has worked on concurrent algorithms and transactional memory for over ten years, most recently, focusing on the implementation of STM for multi-core computers and the design of programming language  ... 
doi:10.2200/s00272ed1v01y201006cac011 fatcat:25d3gvp5zrfqlgpzdzknqouofi

Deconstructing the Tail at Scale Effect Across Network Protocols [article]

Akshitha Sriraman, Sihang Liu, Sinan Gunbay, Shan Su, Thomas F. Wenisch
2017 arXiv   pre-print
Our experimental design eliminates network congestion as a tail-inducing factor.  ...  This paper deconstructs the "tail at scale" effect across TCP-IP, UDP-IP, and RDMA network protocols.  ...  transactions, and n = 5 refers to 99.999% of the total transactions.  ... 
arXiv:1701.03100v2 fatcat:bjgfo5nnd5fubgjta43d2ifbuq

A case for unlimited watchpoints

Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd Austin
2012 Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '12  
We describe a hardware design that stores watchpoints in main memory and utilizes two different on-chip caches to accelerate performance.  ...  As an example of the power of such a system, it is possible to use watchpoints to accelerate read/write set checks in a software data race detector by nearly 9×.  ...  The authors acknowledge the support of the Gigascale Systems Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program.  ... 
doi:10.1145/2150976.2150994 dblp:conf/asplos/GreathouseXLA12 fatcat:sirwrqqo4zenllc3fn2kpgps6e

A case for unlimited watchpoints

Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd Austin
2012 SIGARCH Computer Architecture News  
We describe a hardware design that stores watchpoints in main memory and utilizes two different on-chip caches to accelerate performance.  ...  As an example of the power of such a system, it is possible to use watchpoints to accelerate read/write set checks in a software data race detector by nearly 9×.  ...  The authors acknowledge the support of the Gigascale Systems Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program.  ... 
doi:10.1145/2189750.2150994 fatcat:tgjib5rsabfidiwgikxdzcgjie

Deconstructing the overhead in parallel applications

Mark Roth, Micah J Best, Craig Mustard, Alexandra Fedorova
2012 2012 IEEE International Symposium on Workload Characterization (IISWC)  
They can stem from synchronization overhead, poor thread scheduling decisions, or contention for hardware resources, such as shared caches.  ...  We present three case studies where analyzing profiling data according to the proposed principle led us to improve performance of three parallel programs by a factor of 6-20×.  ...  or other hardware in the memory system.  ... 
doi:10.1109/iiswc.2012.6402901 dblp:conf/iiswc/RothBMF12 fatcat:jayl4mvrlzhpzji4pt3spa24l4

Energy Aware Persistence

Sudarsun Kannan, Moinuddin Qureshi, Ada Gavrilovksa, Karsten Schwan
2016 Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16  
in a transactional manner.  ...  and a memory management method that reduces energy by trading capacity via less frequent garbage collection.  ...  This work was supported in part by the Intel URO program on software for persistent memories, and by C-FAR, one of the six SRC STARnet Centers, sponsored by MARCO and DARPA.  ... 
doi:10.1145/2967938.2967953 dblp:conf/IEEEpact/KannanQGS16 fatcat:bqpkeh6ocfhmzcscbvogalxz2m

System-on-Chip Design Using High-Level Synthesis Tools

Erdal Oruklu, Richard Hanley, Semih Aslan, Christophe Desmouliers, Fernando M. Vallina, Jafar Saniie
2012 Circuits and Systems  
Hence, in order to demonstrate the fundamental hardware design concepts, a case study is presented.  ...  This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools.  ...  (www.xilinx.com) and Synopsys (www.synopsys.com) for their valuable support.  ... 
doi:10.4236/cs.2012.31001 fatcat:gj4k4n4blnhxhf4hag5jqsz2yi

Deconstructing Blockchains: A Comprehensive Survey on Consensus, Membership and Structure [article]

Christopher Natoli, Jiangshan Yu, Vincent Gramoli, Paulo Esteves-Verissimo
2019 arXiv   pre-print
Through this paper, we set out to explain blockchains in a simple way, taming that complexity through the deconstruction of the blockchain into three simple, critical components common to all known systems  ...  It is no exaggeration to say that since the introduction of Bitcoin, blockchains have become a disruptive technology that has shaken the world.  ...  Scalability of decentralized distributed systems is a major problem area for a number of systems with a numerous proposals for improvements.  ... 
arXiv:1908.08316v1 fatcat:aca6xwvfmrb2le35z77wqjv5sq

Deconstructing process isolation

Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen Hunt, James Larus
2006 Proceedings of the 2006 workshop on Memory system performance and correctness - MSPC '06  
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions.  ...  Singularity is a new operating system that uses software mechanisms to enforce process isolation.  ...  Hardware for HIPs does not come for free, though its costs are diffused and difficult to quantify: Virtual memory systems (with the exception of software-only systems such as SPUR [46] ) rely on a hardware  ... 
doi:10.1145/1178597.1178599 dblp:conf/ACMmsp/AikenFHHL06 fatcat:phhrwc2gb5efjgz5sjuf4c3pam

NanoStreams: Codesigned microservers for edge analytics in real time

Giorgis Georgakoudis, Charles Gillan, Ahmad Hassan, Umar I. Minhas, Ivor Spence, George Tzenakis, Hans Vandierendonck, Roger Woods, Dimitrios S. Nikolopoulos, Murali Shyamsundar, Paul Barber, Matthew Russell (+8 others)
2016 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)  
From the OS perspective, allocating memory on a hybrid memory system is similar to allocating memory in a nonuniform memory architecture (NUMA).  ...  Every NUMA region is split into a DRAM region and an NVM region. As such, the OS and system libraries utilise the same memory allocation algorithm for either type of memory.  ... 
doi:10.1109/samos.2016.7818346 dblp:conf/samos/GeorgakoudisGHM16 fatcat:d7ljernsljftzc6s64a54z53cy
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