A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
A 14b 70MS/s 3-stage pipeline ADC in a 0.13um CMOS process employs signal insensitive 3-D fully symmetric capacitors for high matching accuracy without any calibration scheme. ... , and consumes 235mW at 70MS/s. ... The proposed 14b 70MS/s 2.5V 0.13um CMOS ADC employs signal insensitive 3-D fully symmetric capacitor layout techniques in two multiplying DACs (MDACs) to obtain high matching accuracy without any calibration ...doi:10.1109/cicc.2006.320860 dblp:conf/cicc/ChoLCLMK06 fatcat:gxqncjbfl5dftabuvqer3hxvee