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A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

E. Laskin, S.P. Voinigescu
2006 IEEE Journal of Solid-State Circuits  
The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s.  ...  It was fabricated in a 150-GHz SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane.  ...  Beerkens for their support and STMicroelectronics for fabrication. The authors also thank NSERC and Micronet for financial support, OIT and CFI for test equipment, and CMC for CAD tools and support.  ... 
doi:10.1109/jssc.2006.878112 fatcat:3pjasxod45dzxijuw5dpnys66u

Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies

D. L. Harame, K. M. Newton, R. Singh, S. L. Sweeney, S. E. Strang, J. B. Johnson, S. M. Parker, C. E. Dickey, M. Erturk, G. J. Schulberg, D. L. Jordan, D. C. Sheridan (+6 others)
2003 IBM Journal of Research and Development  
The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits.  ...  To enable this, IBM has in place a mature project infrastructure consisting of predictive device models, complete rf characterization, statistical and scalable compact models that are hardware-verified  ...  Acknowledgments The authors wish to acknowledge the many individuals in IBM who contributed to the SiGe program and are responsible for the current position of SiGe technology in the marketplace.  ... 
doi:10.1147/rd.472.0139 fatcat:pejbk72rafbfxkagylkctnet24

A BiCMOS front-end system with binary delay line for capacitive detector read-out

J. Wulleman
1998 IEEE Journal of Solid-State Circuits  
The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields.  ...  Pre-rad, the binary delay line has a delay of 2.1 s at 40 MHz and a power consumption of 450 W/channel for a four-channel design.  ...  A BiCMOS Front-End System with Binary Delay Line for Capacitive Detector Read-Out I.  ... 
doi:10.1109/4.654941 fatcat:rouwvljvvfhldgt4egyfy7xf5y

Computer-aided design of analog and mixed-signal integrated circuits

G.G.E. Gielen, R.A. Rutenbar
2000 Proceedings of the IEEE  
But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing  ...  need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits.  ...  The technology shift from bipolar to CMOS (or BiCMOS) has been apparent in most applications.  ... 
doi:10.1109/5.899053 fatcat:2kjzezalevhuzayfrkykyvm5py

ComputerAided Design of Analog and MixedSignal Integrated Circuits [chapter]

2009 Computer-Aided Design of Analog Integrated Circuits and Systems  
But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing  ...  need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits.  ...  The technology shift from bipolar to CMOS (or BiCMOS) has been apparent in most applications.  ... 
doi:10.1109/9780470544310.ch1 fatcat:nz4on5owvvdxbneeuh3aqrkkfe

Status and trends of power semiconductor device models for circuit simulation

R. Kraus, H.J. Mattausch
1998 IEEE transactions on power electronics  
From 1988 to 1990, he was involved in the design of DRAM's and SRAM's in BICMOS technology and the modeling of MOS transistors for analog applications.  ...  From 1984 to 1988, he worked on the design and analysis of DRAM circuits.  ...  A key element for achieving such an upgrade in CAD methodology is the availability of high-quality power device models for circuit simulation.  ... 
doi:10.1109/63.668107 fatcat:cudcjpe3xjbztoiz2dcnp2aeau

High-Frequency Circuit Design Oriented Compact Bipolar Transistor Modeling with HICUM

M. SCHROTER
2005 IEICE transactions on electronics  
A model hierarchy is introduced, that addresses a variety of requirements encountered during the increasingly complicated task of designing analog and high-frequency circuits. key words: bipolar transistors  ...  , compact modeling, HICUM * The acronym HBT is used here for bipolar transistors in general, i.e. including homojunction transistors which are a special case of HBTs.  ...  During circuit design often additional device configurations are requested to be added to the library, or models with continuously differentiable scaling properties are even required for circuit optimizers  ... 
doi:10.1093/ietele/e88-c.6.1098 fatcat:z3uir67e4vet7ac3afdblluv4y

The future of solid-state electronics

William F. Brinkman, Mark R. Pinto
2002 Bell Labs technical journal  
Baumann for providing the TEM images used in the figures, and R. M. Camarda for furnishing the schematic of the Scalpel mask.  ...  design procedures and for capturing general trends.  ...  Abbreviations, Acronyms, and Terms AFM-atomic force microscopy ASIC-application-specific integrated circuit BiCMOS-bipolar CMOS CHINT-charge injection transistor CMOS-complementary metal-oxide semiconductor  ... 
doi:10.1002/bltj.2083 fatcat:auwjdokrmbahxc7op2jksmsxfi

Small-signal and power evaluation of novel BiCMOS-compatible short-channel LDMOS technology

O. Bengtsson, A. Litwin, J. Olsson
2003 IEEE transactions on microwave theory and techniques  
Finally I would like to express my deepest gratitude to the University of Gävle and especially the research board of science and technology "NT-Nämnden" for providing financing that gave me the possibility  ...  to conduct this work.  ...  Technology CAD Technology CAD or TCAD is a physics based simulation tool used for prefabrication process and device optimization.  ... 
doi:10.1109/tmtt.2003.808697 fatcat:dw4odvezybeo7pqfy4ikx34dgq

A Fundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor With Integrated Antenna

Ioannis Sarkas, Juergen Hasch, Andreea Balteanu, Sorin P. Voinigescu
2012 IEEE transactions on microwave theory and techniques  
Index Terms--band, distance sensor, Doppler radar, integrated antenna, in-phase/quadrature (IQ) receiver, 120-GHz transceiver, phase calibration circuit, radar sensor, SiGe BiCMOS.  ...  Several experiments were conducted through the air over distances of up to 2.1 m with a focusing lens placed above the packaged chip.  ...  Sautreuil for discussions on the SiGe BiCMOS process, and J.  ... 
doi:10.1109/tmtt.2011.2176504 fatcat:onofr3eq55cmtbjfgt4vj2erom

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
Hence, the subthreshold circuit has characteristics of a bipolar transistor [3] so that delay in the ideal subthreshold operation can be approximated to the base transit time in the bipolar transistor  ...  In addition to technology scaling, devices need to be optimized for subthreshold operations for higher operating frequency since conventional devices, which are optimized for the operation in a strong  ...  , and scaling issues for bipolar/BiCMOS devices and circuits.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

Radiation Tolerant Electronics

Paul Leroux
2019 Electronics  
Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits  ...  Acknowledgments: I would like to thank all of the researchers who submitted articles to this Special Issue for their excellent contributions.  ...  Acknowledgments: Thanks to the the National Centre for Accelerators (CNA)-Spain, and Los Alamos Neutron Science Center (LANSCE)-USA for all the support in the the irradiation campaigns.  ... 
doi:10.3390/electronics8070730 fatcat:wjo5prr5xjeqtlhxlj4kqz5st4

Active Filters: Tools and Techniques for Active Filter Design [chapter]

Laurent Billonnet, Bernard Jarry, Bruno Barelaud
2005 Encyclopedia of RF and Microwave Engineering  
ANALYTICAL TOOLS AND PROCEDURES FOR ACTIVE FILTER DESIGN Numerical CAD Optimization Tools Since 1980, scientific production on microwave filters has grown extensively.  ...  The term SiGe BiCMOS HBT refers to heterojunction bipolar transistor, for which the base is doped with germanium.  ... 
doi:10.1002/0471654507.eme579 fatcat:js5lko2r45ekjgklbvxyu34t4e

Future trends in microelectronics - reflections on the road to nanotechnology

1997 Precision engineering  
Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining  ...  Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for  ...  The authors would like to thank the following people for both technical assistance and critical comments: Rolf Landauer, John Heidenreich, J. Frank White, John Hummel, Steve Greco, C.-K.  ... 
doi:10.1016/0141-6359(97)90048-9 fatcat:j7blw4wn6zbitmoqqffj46g54e

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

R. M. Averill, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T. J. McPherson, G. A. Northrop (+4 others)
1999 IBM Journal of Research and Development  
This concept is a key requirement necessary to achieve high frequency of operation, meet area targets within the defined architecture, and ensure a robust and reliable design for transistor counts from  ...  A concept known as chip integration, which includes a combination of critical physical design techniques such as floorplanning, power distribution, high-speed clock design, wiring methodologies, circuit  ...  The tuning process consists of multiple runs of the clock tuning program to adjust the widths of the wires to optimize skew and delay.  ... 
doi:10.1147/rd.435.0681 fatcat:ywbcgllmcfh7zl5s5hvxw6hfca
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