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A Burst Scheduling Access Reordering Mechanism

Jun Shao, Brian T. Davis
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
Using a revised M5 simulator with an accurate SDRAM module, the burst scheduling access reordering mechanism is proposed and compared to conventional in order memory scheduling as well as existing academic  ...  Burst scheduling also outperforms Intel's patented out of order memory scheduling and the row hit access reordering mechanism by 11% and 6% respectively.  ...  Simulated Access Reordering Mechanisms Besides BkInOrder scheduling, three existing access reordering mechanisms, RowHit, Intel and Intel RP, are simulated and compared with burst scheduling.  ... 
doi:10.1109/hpca.2007.346206 dblp:conf/hpca/ShaoD07 fatcat:4zi23qhykfgvlmz34l2ymzqf7m

Novel Memory Access Scheduling Algorithms for a Surveillance System

Slo-Li Chu, Min-Jen Lo
2013 Applied Mathematics & Information Sciences  
By integrating Access Buffers, Frontend Scheduler, Reorder Block, Backend Scheduler, and two scheduling algorithms, SAMS can provide a sufficient memory bandwidth for the streaming processors with high  ...  This study proposes novel memory accessing scheduling algorithms, with a corresponding memory controller, called Self-Adjustable Memory System (SAMS), for a multiple-channel streaming systemon-a-chip.  ...  Scheduler, Reorder Block, and Backend Scheduler into a single memory system.  ... 
doi:10.12785/amis/070251 fatcat:iacdjjodazgcrma7qxzum7gwhm

Reordering Memory Bus Transactions for Reduced Power Consumption [chapter]

Bruce R. Childers, Tarun Nakra
2001 Lecture Notes in Computer Science  
Using MPOWER, we measured the effectiveness of reordering memory accesses on switching activity.  ...  This paper also describes a practical hardware scheme for reordering the elements within a cache line to reduce switching activity.  ...  In this case, the bus is not driven following a burst transfer (i.e., a cache line), and the scheduling scope is limited to a cache line.  ... 
doi:10.1007/3-540-45245-1_10 fatcat:ndcksq4o7fhadgglbc5d2botva

Performance Issues in Optical Burst/Packet Switching [chapter]

Davide Careglio, Javier Aracil, Siamak Azodolmolky, Joan García-Haro, Sebastian Gunreben, Guoqiang Hu, Mikel Izal, Andreas Kimsas, M. Klinkowski, Martin Köhn, Eduardo Magaña, Daniel Morató (+7 others)
2009 Lecture Notes in Computer Science  
recurso Access to the published version may require subscription 7 Performance issues in optical burst/packet switching Abstract.  ...  Esta es la versión de autor de la comunicación de congreso publicada en: This is an author produced version of a paper published in: El acceso a la versión del editor puede requerir la suscripción del  ...  The burst scheduler uses a void filling-based algorithm.  ... 
doi:10.1007/978-3-642-01524-3_8 fatcat:vozuuja5zbaaliaaa4wxex6dai

Architecture---The design space of data-parallel memory systems

Jung Ho Ahn, Mattan Erez, William J. Dally
2006 Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06  
We identify the interference between concurrent read and write memory-access threads, and bank conflicts, both within a single thread and across multiple threads, as the most critical factors affecting  ...  We advocate either relying on multiple concurrent accesses from a single memory-reference thread only, while sacrificing load-balance, or introducing new hardware to maintain both locality of reference  ...  Memory Access Scheduling Memory access scheduling is used to reorder the DRAM commands associated with pending memory accesses to enhance locality and optimize throughput.  ... 
doi:10.1145/1188455.1188540 dblp:conf/sc/AhnED06 fatcat:3t5guyrblnbsdgz2kqn3kgwa2q

The Design Space of Data-Parallel Memory Systems

Jung Ahn, Mattan Erez, William Dally
2006 ACM/IEEE SC 2006 Conference (SC'06)  
We identify the interference between concurrent read and write memory-access threads, and bank conflicts, both within a single thread and across multiple threads, as the most critical factors affecting  ...  We advocate either relying on multiple concurrent accesses from a single memory-reference thread only, while sacrificing load-balance, or introducing new hardware to maintain both locality of reference  ...  Memory Access Scheduling Memory access scheduling is used to reorder the DRAM commands associated with pending memory accesses to enhance locality and optimize throughput.  ... 
doi:10.1109/sc.2006.61 fatcat:sswngrxxozdprmmdwclxlfrhem

A Network Layer Approach to Enable TCP over Multiple Interfaces

Kameswari Chebrolu, Bhaskaran Raman, Ramesh R. Rao
2005 Wireless networks  
To improve overall performance of TCP, we take a two-pronged approach: (1) We propose a scheduling algorithm that partitions traffic onto the different paths (corresponding to each interface) such that  ...  In this paper, we motivate the advantages of simultaneous use of multiple interfaces and present a network layer architecture that supports diverse multi-access services.  ...  a burst of packets at the TCP sender.  ... 
doi:10.1007/s11276-005-3518-5 fatcat:5ubu3igmqvbtrnm36ijycmkyru

Implementation of Interface between AXI and DDR3 memory Controller for SoC

Onteru Sreenath, Syed kareemsaheb
2015 International Journal Of Engineering And Computer Science  
While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.  ...  The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access.  ...  By using burst mode access in a memory row, current SDRAM architectures can reduce the overhead due to access latency.  ... 
doi:10.18535/ijecs/v4i8.66 fatcat:k54ogfa2y5fd5fhl3kewghadmm

Source-ordering for improved TCP performance over load-balanced optical burst-switched (OBS) networks

Bharat Komatireddy, Neal Charbonneau, Vinod M. Vokkarane
2009 Photonic network communications  
We propose a source-ordering mechanism that significantly improves TCP throughput over a loadbalanced OBS network.  ...  Recent advances in optical switching technology allows for the creation of networks in which data bursts are switched optically at each node, offering a greater degree of flexibility suitable for handling  ...  Only burst scheduling needs to be modified at the ingress.  ... 
doi:10.1007/s11107-009-0205-y fatcat:75ghtcak6fbofa446zxzslixxy

Source-ordering for improved TCP performance over load-balanced Optical burst-switched (OBS) networks

Bharat Komatireddy, Vinod M. Vokkarane
2007 2007 Fourth International Conference on Broadband Communications, Networks and Systems (BROADNETS '07)  
We propose a source-ordering mechanism that significantly improves TCP throughput over a loadbalanced OBS network.  ...  Recent advances in optical switching technology allows for the creation of networks in which data bursts are switched optically at each node, offering a greater degree of flexibility suitable for handling  ...  Only burst scheduling needs to be modified at the ingress.  ... 
doi:10.1109/broadnets.2007.4550430 dblp:conf/broadnets/KomatireddyV07 fatcat:blekc5e5czgy3a5py3edtovhja

Application Specific Memory Access, Reuse and Reordering for SDRAM [chapter]

Samuel Bayliss, George A. Constantinides
2011 Lecture Notes in Computer Science  
This, combined with reordering of the transactions, allows up to 128x reduction in the memory access time of certain memory-intensive benchmarks.  ...  This paper outlines an automated procedure for generating an application-specific memory hierarchy which exploits reuse and reordering and quantifies the impact this has on memory bandwidth over a range  ...  The third observable mechanism is the reduction in the interleaving of accesses to different arrays.  ... 
doi:10.1007/978-3-642-19475-7_6 fatcat:zeb26g5eovhurgjv7javb5lm7y

An efficient quality-aware memory controller for multimedia platform SoC

Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen
2005 IEEE transactions on circuits and systems for video technology (Print)  
Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation  ...  Index Terms-Memory controller, multimedia application, quality-aware scheduler (QAS).  ...  priority access scheme is based on a round-robin token passing mechanism [12] .  ... 
doi:10.1109/tcsvt.2005.846412 fatcat:izetnphxzbga7kkdtug7ptlr5a

Optimal Packet Aggregation Scheduling in Wireless Networks

Alper Sinan Akyurek, Tajana Simunic Rosing
2018 IEEE Transactions on Mobile Computing  
This paper gives a state-of-the-art knowledge of bandwidth aggregation and packet reordering in HWN and it is expected that this investigation will be a milestone for further research.  ...  This paper aims to investigate the common scheduling algorithms both adaptive and non-adaptive solutions that have been using in networking and communication field.  ...  A scheduling mechanism is proposed for interactive multimedia transmission over heterogeneous wireless network [41] .  ... 
doi:10.1109/tmc.2018.2826554 fatcat:dg3hzuiyknbonoskrfj4g4tmx4

An analytic behavior model for disk drives with readahead caches and request reordering

Elizabeth Shriver, Arif Merchant, John Wilkes
1998 Performance Evaluation Review  
Modern disk drives read-ahead data and reorder incoming requests in a workload-dependent fashion.  ...  To address this problem we h a v e developed a new analytic model for disk drives that do readahead and request reordering.  ...  size of a burst requests bursty fraction fraction of requests that occur in a burst 0 1 spatial locality measures data span the span range of data accessed bytes request size length of  ... 
doi:10.1145/277858.277906 fatcat:xlr5npdlsfavji3vm6qep7sdsq

An analytic behavior model for disk drives with readahead caches and request reordering

Elizabeth Shriver, Arif Merchant, John Wilkes
1998 Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems - SIGMETRICS '98/PERFORMANCE '98  
Modern disk drives read-ahead data and reorder incoming requests in a workload-dependent fashion.  ...  To address this problem we h a v e developed a new analytic model for disk drives that do readahead and request reordering.  ...  size of a burst requests bursty fraction fraction of requests that occur in a burst 0 1 spatial locality measures data span the span range of data accessed bytes request size length of  ... 
doi:10.1145/277851.277906 dblp:conf/sigmetrics/ShriverMW98 fatcat:aooypbdvnzg6lom4u5nlbydxri
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