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A Hardware-Software Blueprint for Flexible Deep Learning Specialization [article]

Thierry Moreau, Tianqi Chen, Luis Vega, Jared Roesch, Eddie Yan, Lianmin Zheng, Josh Fromm, Ziheng Jiang, Luis Ceze, Carlos Guestrin, Arvind Krishnamurthy
2019 arXiv   pre-print
We propose a flow that performs design space exploration to generate a customized hardware architecture and software operator library that can be leveraged by mainstream learning frameworks.  ...  Next, we propose a runtime system equipped with a JIT compiler for flexible code-generation and heterogeneous execution that enables effective use of the VTA architecture.  ...  For the VTA hardware designs, we use an automated 8-bit integer scaling and translation pass from 32-bit floatingpoint (FP32) with negligible accuracy degradation.  ... 
arXiv:1807.04188v3 fatcat:wpafekkrqzffzfe7vulaa6qnva

GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs [article]

Markus Vogt, Gerald Hempel, Jeronimo Castrillon, Christian Hochberger
2015 arXiv   pre-print
It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly.  ...  In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular.  ...  The authors show a customized GCC compiler for generation of hardware accelerators for a bare-metal soft-core processor.  ... 
arXiv:1509.00025v2 fatcat:a6oygvn5enc7viygzizjmdmntm

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation

Simon Rokicki, Erven Rohou, Steven Derrien
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
To preserve the single ISA programming model, we resort to Dynamic Binary Translation, and use this technique to enable dynamic code specialization for Runtime Reconfigurable VLIWs cores.  ...  Our proposed DBT framework targets the RISC-V ISA, for which both OoO and in-order implementations exist.  ...  Dynamic Binary Translation Dynamic Binary Translation has mainly been used for portability purposes: fast simulation of an instruction set architecture (e.g.  ... 
doi:10.23919/date.2018.8342160 dblp:conf/date/RokickiRD18 fatcat:g5hf657vx5b3xb736kmwnf4fi4

Programmable decoder and shadow threads: Tolerate remote code injection exploits with diversified redundancy

Ziyi Liu, Weidong Shi, Shouhuai Xu, Zhiqiang Lin
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
Specifically, given a piece of (legacy) binary code, we first generate diversified binary versions using an offline binary rewriter and programmable hardware binary translator at runtime.  ...  We present a lightweight hardware framework for providing high assurance detection and prevention of code injection attacks using a lockstep diversified shadow execution.  ...  Specifically, given a piece of (legacy) binary code, we first generate diversified versions by remapping its machine codes through a binary rewriter.  ... 
doi:10.7873/date.2014.064 dblp:conf/date/LiuSXL14 fatcat:xz5olyqgpbhqlmnzuj2ipxzosm

The Bourgeois Gentleman, Engineering and Formal Methods [article]

Thierry Lecomte
2020 arXiv   pre-print
Industrial applications involving formal methods are still exceptions to the general rule.  ...  This article reports some experience about a game changer that is going to seamlessly integrate formal methods into safety critical systems engineering.  ...  -Translation into MIPS Assembly then to HEX binary code, with a specific compiler developed for this purpose (instance I 2 ).  ... 
arXiv:2005.08309v1 fatcat:5hyxy3gplbctljazyft76l5zry

Past Time LTL Runtime Verification for Microcontroller Binary Code [chapter]

Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski
2011 Lecture Notes in Computer Science  
This paper presents a method for runtime verification of microcontroller binary code based on past time linear temporal logic (ptLTL).  ...  We show how to implement a framework that, owing to a dedicated hardware unit, does not require code instrumentation, thus, allowing the program under scrutiny to remain unchanged.  ...  to provide a framework that works on the level of binary code and additionally satisfies the following requirements: Req1: Generality For a verification on the binary code level the target microcontroller  ... 
doi:10.1007/978-3-642-24431-5_5 fatcat:pdmmbanhx5dg7cybtp72ubwlqa

The State of Fault Injection Vulnerability Detection [chapter]

Thomas Given-Wilson, Nisrine Jafri, Axel Legay
2018 Lecture Notes in Computer Science  
Fault injection is a well known method to test the robustness and security vulnerabilities of software.  ...  Further, there is very limited connection between simulation results and hardware experiments.  ...  The latest in automated approaches that can be applied more generally to binary programs are also recalled.  ... 
doi:10.1007/978-3-030-00359-3_1 fatcat:54ovnmm5q5f4dbvirhfk44tjw4

Machine-adaptable dynamic binary translation

David Ung, Cristina Cifuentes
2000 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization - DYNAMO '00  
This research provides for a more general framework for dynamic translations, by providing a framework based on specifications of machines that can be reused or adapted to new hardware architectures.  ...  Dynamic binary translation is the process of translating and optimizing executable code for one machine to another at runtime, while the program is "executing" on the target machine.  ...  UQDBT appears to be a promising model to provide a genetic dynamic binary translation framework.  ... 
doi:10.1145/351397.351414 dblp:conf/dynamo/UngC00 fatcat:3o5n2zhc4zh2beqz6gm5bj7wom

Machine-adaptable dynamic binary translation

David Ung, Cristina Cifuentes
2000 SIGPLAN notices  
This research provides for a more general framework for dynamic translations, by providing a framework based on specifications of machines that can be reused or adapted to new hardware architectures.  ...  Dynamic binary translation is the process of translating and optimizing executable code for one machine to another at runtime, while the program is "executing" on the target machine.  ...  UQDBT appears to be a promising model to provide a genetic dynamic binary translation framework.  ... 
doi:10.1145/351403.351414 fatcat:25wcmpsy6rglnaeltlpjimg64i

CRETE: A Versatile Binary-Level Concolic Testing Framework [chapter]

Bo Chen, Christopher Havlicek, Zhenkun Yang, Kai Cong, Raghudeep Kannavara, Fei Xie
2018 Lecture Notes in Computer Science  
In this paper, we present crete, a versatile binary-level concolic testing framework, which features an open and highly extensible architecture allowing easy integration of concrete execution frontends  ...  We have evaluated the effectiveness of crete on GNU Coreutils programs and TianoCore utility programs for UEFI BIOS.  ...  symbolic executors for automated program analysis at source-level and binary-level.  ... 
doi:10.1007/978-3-319-89363-1_16 fatcat:yo57gft65bamfkhpdbnb7z5uki

NN2CAM: Automated Neural Network Mapping for Multi-Precision Edge Processing on FPGA-Based Cameras [article]

Petar Jokic, Stephane Emery, Luca Benini
2021 arXiv   pre-print
Our mapping tool features automatic translation from a trained Caffe network, arbitrary layer-wise fixed-point precision for both weights and activations, an efficient XNOR implementation for fully binary  ...  We propose an automated deployment framework for DNN acceleration at the edge on field-programmable gate array (FPGA)-based cameras.  ...  HLS compilation to hardware representation The last step of the mapping process consists of translating the framework-internal high-level representation into a hardware description.  ... 
arXiv:2106.12840v1 fatcat:mgbrgszixfdpvajtbkmmga6f2m

ICSREF: A Framework for Automated Reverse Engineering of Industrial Control Systems Binaries [article]

Anastasis Keliris, Michail Maniatakos
2018 arXiv   pre-print
We apply this methodology to develop the modular Industrial Control Systems Reverse Engineering Framework (ICSREF), and instantiate ICSREF modules for reversing binaries compiled with CODESYS, a widely  ...  In this work, we propose a structured methodology that automates the reverse engineering process for ICS binaries taking into account their unique domain-specific characteristics.  ...  Although ICSREF is not a disassembler but a more general framework tailored to PLC binaries, a rough comparison can be made between it and more generic disassembler frameworks that also allow scripting  ... 
arXiv:1812.03478v1 fatcat:yb7nciblmvdj5bviy6vnqtvlly

Formal Verification of Hardware Components in Critical Systems

Wilayat Khan, Muhammad Kamran, Syed Rameez Naqvi, Farrukh Aslam Khan, Ahmed S. Alghamdi, Eesa Alsolami
2020 Wireless Communications and Mobile Computing  
In this paper, we define a lightweight mathematical framework in computer-based theorem prover Coq for describing and reasoning about Boolean algebra and hardware components (logic circuits) modelled as  ...  Hardware components, such as memory and arithmetic units, are integral part of every computer-controlled system, for example, Unmanned Aerial Vehicles (UAVs).  ...  Our gate-level description language provides a general framework for describing combinational circuits.  ... 
doi:10.1155/2020/7346763 fatcat:nwrynuotc5h3zarf5iuri7l4si

Exploring the Heterogeneous Design Space for both Performance and Reliability

Rafael Ubal, Dana Schaa, Perhaad Mistry, Xiang Gong, Yash Ukidave, Zhongliang Chen, Gunar Schirner, David Kaeli
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
We address heterogeneity both in hardware and software, providing a flexible framework that can be easily adapted and extended as new elements in the SoC stack continue to evolve.  ...  In this paper we present a new methodology to address these challenges in a flexible and extensible framework.  ...  ACKNOWLEDGMENTS The authors would like thank AMD, Analog Devices, NVIDIA, Samsung and Qualcomm for supporting this work.  ... 
doi:10.1145/2593069.2596680 dblp:conf/dac/UbalSMGUCSK14 fatcat:i4b2nezub5abbgmmtz32v7mkry

Aggressive Memory Speculation in HW/SW Co-Designed Machines

Simon Rokicki, Erven Rohou, Steven Derrien
2019 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
Recent works have demonstrated the ability to increase their efficiency by using VLIW cores, supported through Dynamic Binary Translation (DBT) to maintain the illusion of a single-ISA system.  ...  Our approach enables fine-grained speculation optimizations thanks to a combination of hardware and software.  ...  A. Dynamic Binary Translation Previous work on Dynamic Binary Translation mainly focused on executing legacy binaries on an in-order VLIW processor [2] , [3] .  ... 
doi:10.23919/date.2019.8715010 dblp:conf/date/RokickiRD19 fatcat:mn6cuvcdwzhltg5m5qq2sj5t5m
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