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A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks [article]

Shuwen Deng, Wenjie Xiong, Jakub Szefer
2019 arXiv   pre-print
The benchmark suite generates the Cache Timing Vulnerability Score which can be used to evaluate how vulnerable a specific cache implementation is to different attacks.  ...  To understand and evaluate all possible types of vulnerabilities in processor caches, this work further presents and implements a new benchmark suite which can be used to test to which types of cache timing-based  ...  Modeling for Cache Timing Attacks The goal of this work is to present the first set of benchmarks which can be used to evaluate all the vulnerabilities of processor caches to timing-based attacks.  ... 
arXiv:1911.08619v1 fatcat:h3lbynlumzbbtg22fisw6f7444

Evaluation of Cache Attacks on Arm Processors and Secure Caches [article]

Shuwen Deng, Nikolay Matyunin, Wenjie Xiong, Stefan Katzenbeisser, Jakub Szefer
2021 arXiv   pre-print
This work shows for the first time a systematic, large-scale analysis of Arm devices and the detailed results of attacks the processors are vulnerable to.  ...  Further, to evaluate a large number of devices, this work leverages a novel approach of using a cloud-based Arm device testbed for architectural and security research on timing channels and runs the benchmarks  ...  The authors would like to acknowledge Amazon Web Services for cloud research credits used for some of the testing.  ... 
arXiv:2106.14054v2 fatcat:hwmgfp5dyjf2nd2xejlvbqqn5i

Benchmarking vulnerability scanners: An experiment on SCADA devices and scientific instruments

Malaka El, Emma McMahon, Sagar Samtani, Mark Patton, Hsinchun Chen
2017 2017 IEEE International Conference on Intelligence and Security Informatics (ISI)  
This research aims to benchmark two state-of-the-art vulnerability assessment tools, Nessus and Burp Suite, in the context of SCADA devices and scientific instruments.  ...  Cybersecurity is a critical concern in society today. One common avenue of attack for malicious hackers is exploiting vulnerable websites.  ...  Attackers can also discover if the DNS server has a specific record cached to determine if the owner has recently visited a specific site for the DNS Snooping vulnerability.  ... 
doi:10.1109/isi.2017.8004879 dblp:conf/isi/ElMSPC17 fatcat:zduvnype5jhr5edbj2cg4aybte

oo7: Low-overhead Defense against Spectre Attacks via Program Analysis [article]

Guanhua Wang, Sudipta Chattopadhyay, Ivan Gotovchits, Tulika Mitra, Abhik Roychoudhury
2019 arXiv   pre-print
Our key contribution is to balance the concerns of effectiveness, analysis time and run-time overheads.  ...  In this paper, we propose oo7, a static analysis approach that can mitigate Spectre attacks by detecting potentially vulnerable code snippets in program binaries and protecting them against the attack  ...  Evaluation on Specint Benchmarks We use SPECint CPU benchmark suite [34] to quantify the performance overhead of oo7 protection mechanism as well as for evaluating the efficacy of our detection and repair  ... 
arXiv:1807.05843v6 fatcat:2ap66rtmf5he7jwqnz57zjoj5y

Rethinking Misalignment to Raise the Bar for Heap Pointer Corruption [article]

Daehee Jang, Jonghwan Kim, Minjoon Park, Yunjong Jung, Hojoon Lee, Brent Byunghoon Kang
2018 arXiv   pre-print
Based on such observations, we design and implement an allocator suited to optimize the performance cost of byte-granularity heap randomization; then evaluate the performance with the memory-intensive  ...  Heap layout randomization renders a good portion of heap vulnerabilities unexploitable. However, some remnants of the vulnerabilities are still exploitable even under the randomized layout.  ...  To evaluate the performance impact of RUMA-compatible modification against Nginx, we benchmarked the request throughput using wrk [44] . The benchmark was repeated 10 times for each case.  ... 
arXiv:1807.01023v3 fatcat:ipjbbsc3ubesnjfs3gr6c326oi

ClepsydraCache – Preventing Cache Attacks with Time-Based Evictions [article]

Jan Philipp Thoma, Christian Niesler, Dominic Funke, Gregor Leander, Pierre Mayr, Nils Pohl, Lucas Davi, Tim Güneysu
2021 arXiv   pre-print
Our solution takes a new approach that assigns each cache entry a random time-to-live to reduce the amount of cache conflicts.  ...  Furthermore, our solution is applicable to large last-level caches which are the most common targets for cache attacks.  ...  Similar to the other benchmark suites evaluated in this paper, the average miss latency reduces for all benchmarks from the MiBench suite as shown in Fig. 20 .  ... 
arXiv:2104.11469v1 fatcat:7yn3erafibcfjkveaxo3px5oze

Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache

Koji Inoue
2006 2006 13th IEEE International Conference on Electronics, Circuits and Systems  
This paper proposes an efficient cache line management algorithm for a security-aware cache architecture (SCache). SCache attempts to detect the corruption of return address values at runtime.  ...  Unfortunately, since the replica data is also a candidate for cache line replacements, SCache does not work well for application programs that cause higher cache miss rates.  ...  ACKNOWLEDGMENTS This research was supported in part by the PREST, Grantin-Aid for Creative Basic Research, 14GS0218, and for Encouragement of Young Scientists (A), 17680005.  ... 
doi:10.1109/icecs.2006.379629 dblp:conf/icecsys/Inoue06a fatcat:5tz4dxr5pzevjbz7jk7rinsmni

Architectural framework for supporting operating system survivability

Xiaowei Jiang, Yan Solihin
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
Through simple but carefully-designed architecture support, we provide OS kernel survivability with low performance overheads (< 5% for kernel intensive benchmarks).  ...  A successful security attack on the kernel has a profound impact that may affect all processes running on it.  ...  Due to vulnerabilities of the OS and the dire consequences of successful security attacks on it, researchers have for a long time studied ways to provide survivability for the OS or the system.  ... 
doi:10.1109/hpca.2011.5749751 dblp:conf/hpca/JiangS11 fatcat:mxnfpr54m5gtnj7wt7lhgxvxry

Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures [article]

Zelalem Birhanu Aweke, Todd Austin
2017 arXiv   pre-print
To provide a means for total protection from timing-based side-channel attacks, we develop Ozone, the first zero timing leakage execution resource for a modern microarchitecture.  ...  A number of approaches to mitigate timing-based side-channel attacks have been proposed including cache partitioning, control-flow obfuscation and injecting timing noise into the outputs of code.  ...  Table II lists references to timing sidechannel attacks for each of the benchmark applications.  ... 
arXiv:1703.07706v1 fatcat:sc7qhi47lzfqzlabm55gnghouy

SPAM: Stateless Permutation of Application Memory [article]

Mohamed Tarek Ibn Ziad, Miguel A. Arroyo, Simha Sethumadhavan
2020 arXiv   pre-print
We further show SPAM's scalability by running a multi-threaded benchmark suite.  ...  The key benefits include resilience against attacks that directly exploit software errors (i.e., spatial and temporal memory safety violations) in addition to attacks that exploit hardware vulnerabilities  ...  We further evaluate SPAM on a pointer and allocation intensive benchmark suite, Olden [65] . We use the big test input as specified by llvm-test-suite.  ... 
arXiv:2007.13808v3 fatcat:a3sa4f5yzfc7fpha6bxbzhmslq

Architectural support for securing application data in embedded systems

Olga Gelbart, Eugen Leontie, Bhagirath Narahari, Rahul Simha
2008 2008 IEEE International Conference on Electro/Information Technology  
The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the system.  ...  We make use of an on-chip FPGA, an architecture that is now commonly available on many processor chips, to build a secure on-chip hardware component that verifies the integrity of application data at run-time  ...  To examine the impact of the cache block size, the analysis was performed on both a 32-byte and 64-byte line caches. The input for evaluation were benchmarks from two different benchmark suites.  ... 
doi:10.1109/eit.2008.4554261 dblp:conf/eit/GelbartLNS08 fatcat:dvalfepaerdptn4qh72l36enie

Energy-security tradeoff in a secure cache architecture against buffer overflow attacks

Koji Inoue
2005 SIGARCH Computer Architecture News  
In this paper, we propose a cache architecture, called SCache, to detect buffer-overflow attacks at run time. Furthermore, the energy-security efficiency of SCache is discussed.  ...  to a well-known lowpower cache.  ...  We assume that the energy consumed for a next-level memory access is ten times larger than that for an L1 cache read access.  ... 
doi:10.1145/1055626.1055638 fatcat:hzduuk6bnzezhivcaw7scut6eu


Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd Austin
2016 Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '16  
Our next-generation CLFLUSH-free rowhammer attack bypasses the cache by manipulating cache replacement state to allow frequent misses out of the last-level cache to DRAM rows of our choosing.  ...  Recent studies have shown serious security concerns due to "rowhammer" attacks, where repeated accesses to a row of memory cause bit flips in adjacent rows.  ...  Acknowledgments We extend special thanks to Mark Seaborn of Google for his many valuable inputs to this work.  ... 
doi:10.1145/2872362.2872390 dblp:conf/asplos/AwekeYQDHOA16 fatcat:gg65wy5mbbehnk4bc4vs4peyai

You Shall Not Bypass: Employing data dependencies to prevent Bounds Check Bypass [article]

Oleksii Oleksenko, Bohdan Trach, Tobias Reiher, Mark Silberstein, Christof Fetzer
2018 arXiv   pre-print
The solutions of this type cause 60% overhead across Phoenix benchmark suite, which compares favorably to the full serialization causing 440% slowdown.  ...  A recent discovery of a new class of microarchitectural attacks called Spectre picked up the attention of the security community as these attacks can circumvent many traditional mechanisms of defense.  ...  Each core has private 32KB L1 and 256KB L2 caches, and all cores share an 8MB L3 cache. We used the largest available datasets provided by the Phoenix benchmark suite.  ... 
arXiv:1805.08506v3 fatcat:zrslzrivdzeohc6rutdkktleeu

HDFI: Hardware-Assisted Data-Flow Isolation

Chengyu Song, Hyungon Moon, Monjur Alam, Insu Yun, Byoungyoung Lee, Taesoo Kim, Wenke Lee, Yunheung Paek
2016 2016 IEEE Symposium on Security and Privacy (SP)  
We ran several benchmarks including the SPEC CINT 2000 benchmark suite. Evaluation results show that the performance overhead caused by our modification to the hardware is low (< 2%).  ...  Memory corruption vulnerabilities are the root cause of many modern attacks.  ...  To evaluate the performance of HDFI, we instantiated it on the Xilinx Zynq ZC706 evaluation board [80] and ran several benchmarks including the SPEC CINT 2000 [68] benchmark suite.  ... 
doi:10.1109/sp.2016.9 dblp:conf/sp/SongMAYLKLP16 fatcat:ludpja4munaybeq7owpvy5b2fq
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