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This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. ... Absolute figures equal to dBc/Hz at 1 kHz and dBc/Hz at 10 MHz are measured from a 104 MHz clock-cleaner. ... A phaselocked loop (PLL) can be used as a clock cleaner because it behaves as a highly selective tunable band-pass filter. ...doi:10.1109/tcsi.2013.2284186 fatcat:gwlyg6lim5czld7pugbg4oycre
A 100 MHz clock-cleaner is demonstrated using ICs fabricated in a 0.5 µm 2P3M CMOS process. ... Experimental results show a 20dB PN improvement at 1 kHz offset frequency with only 3.5% of the capacitor area used in a state-of-the-art cascade-type PLL clock-cleaner. ... A phase-locked loop (PLL) can be used as a clock cleaner because it behaves as a highly-selective tunable band-pass filter. ...doi:10.1109/iscas.2011.5937604 dblp:conf/iscas/PardoA11 fatcat:tdcd7p2qyvcyrafizw6wjgesrm
The clock is set using the on-board 50MHz crystal oscillator. ... In  , a comparison of the effect of radiation on an LC oscillator and a ring oscillator within a PLL was done. ... In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. ...doi:10.3390/electronics8070730 fatcat:wjo5prr5xjeqtlhxlj4kqz5st4