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Applying Multi-Core Model Checking to Hardware-Software Partitioning in Embedded Systems (extended version)
[article]
2015
arXiv
pre-print
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Each instance checks for a different optimum value until the optimization problem is satisfied. ...
We present an alternative approach to solve the hardware (HW) and software (SW) partitioning problem, which uses Bounded Model Checking (BMC) based on Satisfiability Modulo Theories (SMT) in conjunction ...
The basic idea of BMC is to check the negation of a given property at a given depth: given a transition system , a property , and a bound , BMC unrolls the system times and translates it into a verification ...
arXiv:1509.02492v1
fatcat:j3r7b5ontnfmnmkh5555k5eusu
Stressing Symbolic Scheduling Techniques within Aircraft Maintenance Optimization
2008
Journal on Satisfiability, Boolean Modeling and Computation
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The goal of this paper is to develop, analyze and compare different scheduling techniques on a new scheduling/planning problem. The new application domain is aircraft maintenance. ...
Given a problem described by a number of actions and their relationships, finding a schedule, or a plan, means to find a way to perform all the actions minimizing a specific cost function. ...
Acknowledgments The authors would like to thank the Alenia Aerospace, ISLT -Logistic Engineering, Torino, Italy, for the industrial aircraft maintenance databases used in this paper. ...
doi:10.3233/sat190053
fatcat:o6n35f5y4rbufg43hj7xzie6lm
SAT-Based Verification Methods and Applications in Hardware Verification
[chapter]
2006
Lecture Notes in Computer Science
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This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. ...
We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. ...
Acknowledgements We would like to thank Pranav Ashar for his numerous and valuable contributions to the methods described here, and Kazutoshi Wakabayashi and Akira Mukaiyama for their contributions and ...
doi:10.1007/11757283_5
fatcat:5kb2pmlvjvat5ljeei2fflzufa
Multi-core model checking and maximum satisfiability applied to hardware-software partitioning
2017
International Journal of Embedded Systems
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Additionally, we integrate the νZ into the BMC, making it as a specialized solution for optimization in a single-core environment. ...
The multi-core SMT-based BMC approaches allow initializing many verification instances based on the number of available processing cores, where each instance checks a different optimum value until the ...
The basic idea of BMC is to check the negation of a given property at a given depth: given a transition system M , a property φ, and a bound k, BMC unrolls the system k times and translates it into a verification ...
doi:10.1504/ijes.2017.088044
fatcat:dv4vgde67vejzcv5w462alt6ti
Towards analyzing functional coverage in SystemC TLM property checking
2010
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
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For Electronic System Level (ESL) design SystemC has become the standard language due to its excellent support of Transaction Level Modeling (TLM). ...
Thus, in this paper we consider the problem of functional coverage analysis in formal TLM property checking. ...
analysis approach is also formulated as a BMC problem. ...
doi:10.1109/hldvt.2010.5496658
dblp:conf/hldvt/LeGD10
fatcat:bk4bcznaifcofhtzoxo3ye5heu
A New Formal Verification Approach for Hardware-dependent Embedded System Software
2013
IPSJ Transactions on System LSI Design Methodology
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This paper describes a method to generate a computational model for formal verification of hardwaredependent software in embedded systems. ...
The model can be easily integrated into SAT-based verification environments such as those based on Bounded Model Checking (BMC). ...
A BMC approach formulated like this does not have any explicit view on the actual execution paths of a program. ...
doi:10.2197/ipsjtsldm.6.135
fatcat:2xu5vfvcgjgp5agtwxeqpjrvwe
Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver
2008
2008 IEEE Real-Time and Embedded Technology and Applications Symposium
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In this paper, we formulate and solve the problem of optimal hardware/software partitioning and static task scheduling for a hybrid FPGA/CPU device, with the optimization objective of minimizing the total ...
A runtime reconfigurable FPGA allows part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that hardware tasks can be placed and removed dynamically ...
Cabodi et al [15] developed a Bounded Model-Checking (BMC) formulation of the HLS problem for control-intensive control/dataflow graphs, and used the BerkMin SAT engine to solve the BMC problem. ...
doi:10.1109/rtas.2008.39
dblp:conf/rtas/YuanHG08
fatcat:tyzjgol3szhvjhuy6molkmex7i
Model checking
2009
Communications of the ACM
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CEGAR Loop for sequential circuits called the localization reduction, which was developed by R. ...
CEGAR is used in many software Model Checkers including the SLAM Project at Microsoft [1]. ...
Bounded Model Checking (BMC) of computer hardware using a fast SAT solver is now probably the most widely used Model Checking technique. ...
doi:10.1145/1592761.1592781
fatcat:4gjaorwdd5a25jeyoyethnw3fy
Proving transaction and system-level properties of untimed SystemC TLM designs
2010
Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)
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To detect a violation of the property the approach uses a BMC-based formulation over the outermost loop of the SystemC scheduler. ...
Electronic System Level (ESL) design manages the enormous complexity of todays systems by using abstract models. ...
For the verification task, a BMC formulation over the outermost loop of the scheduler has been developed. ...
doi:10.1109/memcod.2010.5558643
dblp:conf/memocode/GrosseLD10
fatcat:hgomdoejbrdfjozxo5zolwfya4
Bounded Model Checking of Multi-threaded Software using SMT solvers
[article]
2010
arXiv
pre-print
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Here, we describe and evaluate an extension of the ESBMC model checker to support the verification of multi-threaded software with shared variables and locks using bounded model checking (BMC) based on ...
In the lazy approach, we generate all possible interleavings and call the BMC procedure on each of them individually, until we either find a bug, or have systematically explored all interleavings. ...
Kroening for the fruitful discussions about the starting point of this work and J. Rathke for many helpful discussions about multi-process systems. We also thank S. ...
arXiv:1003.3830v1
fatcat:kwwhgvtwqjdi5hsjvwxo6nbzxy
An Evolutionary Approach to Area-Time Optimization of FPGA designs
2007
2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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It starts from a behavioral description written in a common high-level language (for instance C) to automatically produce the register-transfer level (RTL) design in a hardware description language (e.g ...
Moreover, it has been integrated a good cost estimation model to guarantee the quality of the solutions found without requiring a complete synthesis for the validation of each generation, an impractical ...
[14] , that describe a SAT-based formulation of automata-based scheduling and propose a resolution algorithm based on SAT solvers and bounded model checking (BMC). Lakshminarayana et al. ...
doi:10.1109/icsamos.2007.4285745
dblp:conf/samos/FerrandiLPPST07
fatcat:kawzwmtgkzb6rdlwxh3y2ci25e
A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem
2010
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of binate covering problems, hinged within a bounded model checking paradigm ...
As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. ...
Contributions This paper includes the following contributions. 1) A new SAT-based formulation for the task graph costoptimal scheduling problem. ...
doi:10.1109/tcad.2010.2061631
fatcat:zgilz4krejf5fdibv7ipahmcqa
VFFVA: dynamic load balancing enables large-scale flux variability analysis
2020
BMC Bioinformatics
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Conclusions VFFVA exploits the parallel capabilities of modern machines to enable biological insights through optimizing systems biology modeling. ...
To characterize the full metabolic spectrum of such systems, Fast Flux Variability Analysis (FFVA) is commonly used in parallel with static load balancing. ...
providing a free academic version of ILOG CPLEX. ...
doi:10.1186/s12859-020-03711-2
pmid:32993482
pmcid:PMC7523073
fatcat:fhqdyinznrfzfpnlddh4oihgni
A Novel Smart Energy Management as a Service over a Cloud Computing Platform for Nanogrid Appliances
2020
Sustainability
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There are two components of the proposed system: software and hardware. The hardware is composed of a base station unit (BSU) and many terminal units (TUs). ...
The proposed strategy automatically responds to power factor correction, to protective home appliances, and to price-based demand response programs to combat the major problem of the demand response programs ...
The key contributions are summed up here:
1. We formulate the energy management and sharing economy problem and present the optimal approach to tackle this problem based on cloud computing.
2. ...
doi:10.3390/su12229686
fatcat:scf3eoc56nfvdjwkkipxg4uaxq
A Novel Real-Time Electricity Scheduling for Home Energy Management System Using the Internet of Energy
2021
Energies
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This paper presents a novel scheduling scheme for the real-time home energy management systems based on Internet of Energy (IoE). ...
A two-level communication system connects the microgrid system, implemented in MATLAB, to the cloud server. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/en14113191
fatcat:mnyt4oorqvgc7fhx6hqodfqamu
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