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2021 IEEE Journal of Solid-State Circuits  
Li 179 A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS ........................................................................  ...  Kim, and J.-B. Lee 212 A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs .......  ... 
doi:10.1109/jssc.2020.3042769 fatcat:wyozmhv4ibcxxnubdhwl7g4zui

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell [article]

Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2021 arXiv   pre-print
The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight and 4-bit output convolution neural network (CNN).  ...  The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-and-accumulate (MAC) computations simultaneously.  ...  [19] stores multi-bit signed numbers in a 2T-2M bit-cell, and uses ADC with adjustable precision to meet different computing requirements. In [20] , the multi-bit input is split and computed.  ... 
arXiv:2110.03937v1 fatcat:ovok4fvmjnbfhc7msakfgpqgyq