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Advanced components and sub-system solutions for 40 Gb/s transmission

R. DeSalvo, A.G. Wilson, J. Rollman, D.F. Schneider, L.M. Lunardi, S. Lumish, N. Agrawal, A.H. Steinbach, W. Baun, T. Wall, R. Ben-Michael, M.A. Itzler (+4 others)
2002 Journal of Lightwave Technology  
With the commissioning of the latest 10-Gb/s systems, vendors are now in the process of developing architectures for their next-generation products. 40-Gb/s components and subsystems are currently in development  ...  In order to realize 40-Gb/s transmission, new component and subsystem developments are crucial.  ...  The OIF SXI-5 standard (oif2001.149) describes the electrical properties of these data signals. Fig. 31 illustrates the deskew functionality of the 40-Gb/s SERDES.  ... 
doi:10.1109/jlt.2002.806782 fatcat:5k2fwmca6jhwtjufs7myknraha

FPGA Implementation of Fixed-Latency Gigabit Serial Links for Muon Spectrometer at the ATLAS Experiment

Vadhiraj Kulkarni
2018 International Journal for Research in Applied Science and Engineering Technology  
INTRODUCTION A Multi-Gigabit Transceiver (MGT) is a SerDes capable of operating at serial bit rates above 1 Gigabit/second.  ...  Latency variations may come from both the serial and parallel sections of a SerDes device.  ...  This architecture is based on latest generation Xilinx FPGA with high speed serial transceivers in the multi Gb/s domain.  ... 
doi:10.22214/ijraset.2018.5467 fatcat:znestkmu2fgq7fbhlwbuahukmm

Development of Framer/Deframer for 5Gbps JESD204B Soft IP

Ingrid B. Escabal, Edzel G. Raffiñan, Jefferson A. Hora
2018 International Journal of Engineering & Technology  
It is recommended that the full system's other blocks, and the testbench for the JESD204B and other soft IP products be investigated to operate at a higher clock frequency without violating the timing  ...  Acknowledging also the funding support of USAID-STRIDE and DOST-PCIEERD for the Microelectronics Laboratory IC Design tools.  ...  This is a serialized interface using a 3.125-Gb/s link rate, and introduces coding and framing, which removes the need for a separate data clock.  ... 
doi:10.14419/ijet.v7i2.11.11000 fatcat:ryurmav6wzfynfdtyfst5c6luy

A novel 3D stacking approach for chip-to-chip interconnects [article]

P Pinxiang Duan, HJS Harm Dorren, O Oded Raz
2014
Acknowledgements Last four years has been a bitter and sweet journey for me. I am so grateful to be guided, companied, and helped by many people.  ...  The power consumption of a 3D stacked receiver in units of mW/Gb/s is 9 mW/Gb/s at 10 Gb/s/channel. The bandwidth density is 13.8 Gb/s/mm 2 or 17.3 Gb/s/mm 2 at 10 Gb/s or at 12.5 Gb/s respectively.  ...  Eye patterns of a 3D stacked receiver chip (a) At 4 Gb/s; (b) At 10 Gb/s.  ... 
doi:10.6100/ir781403 fatcat:sz6gh5qcmbcvxprmfnzuiuocye

Table of Contents – Technical

2021 2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium  
multi-fidelity variant in order to generate a surrogate model of a vector-valued output of a common mode choke.  ...  The proposed technique is demonstrated on a custom designed IC in 180 nm technology.  ... 
doi:10.1109/emc/si/pi/emceurope52599.2021.9559379 fatcat:bqobkpurjje4vb5xpdk56r4lpi

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
in advancing computing by a thousandfold by 2015.  ...  The report itself was drawn from the results of a series of meetings over the second half of 2007, and as such reflects a snapshot in time.  ...  For 100 PB (100 million chips), this reduces to a mere 1 to 320 GB/s per chip.  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m

Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware [article]

Subhankar Pal, University, My
2021
of 12.6x and 17.1x over a high-end CPU, and serves as a stepping stone towards a full SDH system.  ...  This has engendered a programmability-efficiency gap across contemporary platforms.  ...  L1 cache hit rate and utilized memory bandwidth drop to under 40% and 10 GB/s, from 86% and 30 GB/s at 10% density.  ... 
doi:10.7302/2904 fatcat:zraktiwmczc7bkmqqxrvuxdiue

KALYPSO, a novel detector system for high-repetition rate and real-time beam diagnostics

Lorenzo Rota
2018
For example, the net throughput for Gen2 is 4 Gb/s.  ...  In this scenario, one KAPTURE II system will produce a data rate of 6 GB/s.  ... 
doi:10.5445/ir/1000082349 fatcat:anelelnzo5denbe3uco5tqmk3a

Accelerated neuromorphic cybernetics

Korbinian Schreiber
2021
Instead of previously 4 single-ended data pins, the upscaled version contains eight bidirectional full-duplex differential high-speed links, each with a data rate of 1 Gb/s output plus 1 Gb/s input, when  ...  Translated to the BrainScaleS-2 speed-up and encoding, this would correspond to a data rate of about 30 GB s −1 .  ...  Any ideas or quotations from the work of other people, published or otherwise, are fully acknowledged in accordance with the standard referencing practices of the discipline.  ... 
doi:10.11588/heidok.00029324 fatcat:zxu66n4q2bchfkmtajcs4l5mve