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The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. ... Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. ... In this paper, a 5-bit 600-MS/s closed-loop pipeline A/D converter is demonstrated in a 0. 18 a low input capacitance of 170 fF. ...doi:10.1109/jssc.2005.862350 fatcat:b42mbd5vmjeifeunjbkfwuqrpm
A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-m CMOS technology. ... Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. ... CIRCUIT ARCHITECTURE OF DFE AND RECEIVER The receiver is composed of 10 time-interleaved 600-MS/s pipeline A/D converters. ...doi:10.1109/jssc.2006.870911 fatcat:wzdrtg4bpraenmfdlp4u2gyu6q
adaptability have been attained with low-cost digital processing. ... This article reviews one such approach of applying a common communication technique, equalization, to correct for nonlinear distortions in analog circuits, which is analogized as non-ideal communication ... ACKNOWLEDGMENTS The data converter and RF ...doi:10.1109/mcom.2011.5741157 fatcat:pj6u7aao75gs3awdn63rfipohi
., +, JSSC June 2019 1624-1635 A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. ... ., +, JSSC Nov. 2019 3180-3190 A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. ...doi:10.1109/jssc.2019.2956675 fatcat:laiuae7dtragjijttgfatsldmu
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
Yang, “A 600 Ms/s 5-bit pipelined the voltage gain of the amplifier. ... References  and  use an ADC to improve the efficiency at the 6-bit level. ...doi:10.1109/vlsic.2006.1705346 fatcat:vjtlqzv42vbkzmwcey72ddxzuu
Energy Efficiency in Communications and Networks
Energy Efficiency in Communications and Networks 24 digitization level of an electronic system not only to dismiss the fabrication costs but also as a way of reducing its power consumption. ... Using parallelism to exploit the power efficiency of simple structures, a 6-bit ADC working at 600 MS/s based on eight SAR ADCs using a charge redistribution architecture is proposed. ... Moreover, A/D converter (ADC) requirements tend to be more stringent as the analogue functionality is moved to the digital domain. ...doi:10.5772/38356 fatcat:mdddx4o7lvfwjiemumdc2nohhm