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High-performance DRAMs in workstation environments

V. Cuppu, B. Jacob, B. Davis, T. Mudge
2001 IEEE transactions on computers  
Our simulations reveal several things: 1) Current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; 2) bus transmission speed will soon become a primary  ...  These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to~1 or~100).  ...  ACKNOWLEDGMENTS This study grew out of research begun by Brian Davis and extended by Vinodh Cuppu, O È zkan Dikmen, and Rohit Grover in a graduate-level architecture class taught by Professor Jacob in  ... 
doi:10.1109/12.966491 fatcat:r4glk3j7unerpkkmuetfwl5yeq

Architecture design of video processing systems on a chip [article]

Jaspers, EGT (Egbert), With, PHN (Peter) De, Meerbergen, JL (Jef) Van, Eijndhoven, JTJ (Jos) Van
2003
The crossbar network supports up to 4.2 GByte/s bandwidth on-chip, consisting of 2.4 GB/s data and 1.8 GB/s instruction traffic.  ...  and the double 16-bit direct RAMBUS interface which supports a bandwidth up to 3.2 GByte/s.  ...  With the Row Address Strobe (RAS) line, the Column Address Strobe (CAS), the Chip Select (CS), and the Write Enable (WE), commands can be issued like select row, read from a column address, write to a  ... 
doi:10.6100/ir565191 fatcat:5jenm43t5jg7njjhdtxhx42tua