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A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

Sung Bae Park, Young Wug Kim, Young Gun Ko, Kwang Il Kim, Il Kwon Kim, Hee-Sung Kang, Jin Oh Yu, Kwang Pyuk Suh
1999 IEEE Journal of Solid-State Circuits  
A 0.25-m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm 2 silicon die has been developed  ...  Index Terms-Cascode voltage switch logic (CVSL), chemical mechanical polishing (CMP), circuits, CMOS, critical path, C-V, dynamic CMOS circuit design, floating body effect (FBE), fully depleted, microprocessor  ...  A 0.25-m, four-layer-metal, 1.5-V, 600-MHz, fully depleted silicon-on-insulator (FD-SOI) CMOS 64-bit microprocessor [1] integrating 9.66 million transistors on a 209mm silicon die has been developed  ... 
doi:10.1109/4.799847 fatcat:5xz7wlnsfveybagvno4gqzypum

The microprocessor today

M. Slater
1996 IEEE Micro  
) 500 200 225 250 110 180 160* 200 180 200 Cache size (Kbytes) 8/8/96 32/32 32/32 16/16 16/8 None 64/64 32/32 32/32 8/8 Issue rate 4 4 4 4 2 4 2 4 2 3 (instr.  ...  The level-two cache chip, which Intel makes in both 256-and 512-Kbyte versions, delivers 64 bits per clock cycle, even with CPU clock speeds up to 200 MHz.  ...  A well-known speaker on microprocessor technology and system trends, Slater is also a columnist for Electronic Engineering Times, Nikkei Electronics Asia, and Computer Shopper.  ... 
doi:10.1109/mm.1996.546563 fatcat:2crlavzi3fhh3otclfte3nprpu

The history of the microprocessor

Michael R. Betker, John S. Fernando, Shaun P. Whalen
2002 Bell Labs technical journal  
Shipped in early 1993, the 60-MHz Pentium was a 32-bit superscalar CPU with a 64-bit external bus and two integer units.  ...  Alpha began with a 64-bit architecture and PowerPC601 defined a 32/64-mode bit that would allow 64-bit processors in the future.  ... 
doi:10.1002/bltj.2082 fatcat:w2ilifumlzeotdhnncopefkxkm

A 200-MHz 64-b dual-issue CMOS microprocessor

D.W. Dobberpuhl, R.T. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R.A. Conrad, D.E. Dever, B. Gieseke, S.M.N. Hassoun, G.W. Hoeppner (+11 others)
1992 IEEE Journal of Solid-State Circuits  
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation.  ...  Power dissipation is 30 W at 200-MHz operation.  ...  INTRODUCTION RISC-style microprocessor has been designed and A tested that operates up to 200 MHz.  ... 
doi:10.1109/4.165336 fatcat:zugbyrtgobdzvdiyotfuck5huq

Circuit Techniques for Leakage Reduction [chapter]

2018 Low-Power Electronics Design  
In 1992, however, the first very fast microprocessor, Alpha, which ran at 200 MHz, consumed about 30 watts [26] .  ...  Rockwell proposed the 8-bit PPS-8 and 4-bit PPS-4 microprocessors. National Semiconductor presented a 16-bit machine called PACE, while Signetics proposed its 2650 8-bit microprocessor.  ... 
doi:10.1201/9781420039559-19 fatcat:e7eeytdq2rba3d2erlvbyqtkn4

Implementation of a third-generation 1.1-GHz 64-bit microprocessor

G.K. Konstadinidis, K. Normoyle, Samson Wong, S. Bhutani, H. Stuimer, T. Johnson, A. Smith, D.Y. Cheung, F. Romano, Shifeng Yu, Sung-Hun Oh, V. Melamed (+10 others)
2002 IEEE Journal of Solid-State Circuits  
This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s offchip memory bandwidth, and a new 200-MHz JBus interface that supports one to four processors  ...  The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.  ...  It is a 128-bit bus shared between address and data, which can run up to speeds of 200 MHz with a peak bandwidth of 3.2 GB/s.  ... 
doi:10.1109/jssc.2002.803951 fatcat:listejldurdd3ijvnh2lxkuvny

BEE2 A High-End Reconfigurable Computing System

Chen Chang, J. Wawrzynek, R.W. Brodersen
2005 IEEE Design & Test of Computers  
Using a 128-tap 4-channel PFB implemented in the control FPGA, the 800-MHz complex, dual polarization input signal stream is split into four 200-MHz 8-bit complex, dual polarization streams; each stream  ...  The design organizes the four DIMMs into four independent DRAM channels, each running at 200 MHz (400 DDR) with a 72-bit data interface (for a 64-bit data width without error-correcting code).  ...  Direct questions and comments about this article to Chen Chang, 2108 Allston Way, Suite 200, Berkeley, CA 94704; chenzh@eecs.berkeley.edu.  ... 
doi:10.1109/mdt.2005.30 fatcat:mbmzueobdbdqteji63dnf3kkjy

A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

Gianfranco Gerosa, Steve Curtis, Mike D'Addeo, Bo Jiang, Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed Taufique, Haytham Samarchi
2008 2008 IEEE Asian Solid-State Circuits Conference  
units, x86 front end execution unit, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB).  ...  The design contains 47 million transistors in a die size under 25 mm manufactured in a 9-metal 45 nm CMOS process with optimized transistors for low leakage.  ...  point execution units, x86 front end execution unit, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) Front-Side-Bus (FSB).  ... 
doi:10.1109/asscc.2008.4708718 fatcat:s75igiqee5elva2crdciwgk2zi

Three generations of asynchronous microprocessors

A.J. Martin, M. Nystrom, C.G. Wong
2003 IEEE Design & Test of Computers  
Using a new theory of energy complexity and new synthesis tools, we expect 0.5 nJ per instruction at 200 MIPS (in 0.18-µm CMOS at 1.8 V) [3] .  ...  A decade later, we designed the MiniMIPS, an asynchronous version of the 32-bit MIPS R3000 microprocessor.  ...  cpu+fpu) 32 0.8 40 6 R4600 64 0.64 150 0.0719 4.8 2.1 7 21064 64 0.6 200 0.469 23.5 2.1 8 R4400 64 0.6 150 0.234 15.6 7.0 9 SH7708 16/32 0.5 60 0.018 3 8.3 10 P6 32 0.6  ... 
doi:10.1109/mdt.2003.1246159 fatcat:lwsrz6cudng2jhlytgnpcjffqe

A 400-MHz S/390 microprocessor

C.F. Webb, C.J. Anderson, L. Sigal, K.L. Shepard, J.S. Liptay, J.D. Warnock, B. Curran, B.W. Krumm, M.D. Mayo, P.J. Camporese, E.M. Schwarz, M.S. Farrell (+11 others)
1997 IEEE Journal of Solid-State Circuits  
A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns).  ...  The microprocessor features two instruction units (IU's), two fixed point units (FXU's), two floating point units (FPU's), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit  ...  The microprocessor operated in a 10 2 way system at frequencies up to 411 MHz. Leon Sigal received the B.S. degree in biomedical Fig. 1 . 1 A 400-MHz S/390 CMOS microprocessor micrograph.  ... 
doi:10.1109/4.641686 fatcat:qkufxt4n4faulikavu6aqxoijm

CGaAs PowerPC FXU

Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Manufactured in Motorola's 0.5−µm Complementary Gallium Arsenide process, the device operates from 0.9 to 1.9 V with a nominal frequency of 25 MHz at 1.3 V, dissipating 274 mW.  ...  The development of a PowerPC TM fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described.  ...  Since the buses were mixed between 200-MHz and 400-MHz boards, they all had to be run in 200-MHz mode.  ... 
doi:10.1145/337292.337760 dblp:conf/dac/DrakeBGKPGSB00 fatcat:ykfhfiwq4fazvjqkcbf54d7u4i

A 100-MIPS GaAs asynchronous microprocessor

J.A. Tierno, A.J. Martin, D. Borkovic, Tak Kwan Lee
1994 IEEE Design & Test of Computers  
It is the easiest to manufacture, provides the highest density (about 100,000 transistors on a chip), and, for clock frequencies of more than 200 MHz, has a better power-delay product than CMOS.  ...  The microprocessor The microprocessor, a 16-bit, pipelined RISC (reduced instruction-set computer), is a modified version of the 1989 CMOS design.  ... 
doi:10.1109/54.282444 fatcat:etpfdn4ufjae7jkb4owxmrfqsi

A participant's perspective

R.G. Daniels
1996 IEEE Micro  
The "father" of the 6805 MCU relates his role in the history of the microprocessor.  ...  There are other existing works for true historians; for example, The Microprocessor: A Biography and Microprocessor Report's special issue, "Celebrating the 25th Anniversary of the Microprocessor."  ...  Special thanks go to Federico Faggin for beginning the beginning of the microprocessor age-and for inviting me to write this article.  ... 
doi:10.1109/40.546562 fatcat:sbbjxyuplbbvhmyenfgox6wd2q

High-performance microprocessor design

P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon
1998 IEEE Journal of Solid-State Circuits  
Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design.  ...  Index Terms-Alpha, CMOS digital integrated circuits, computer architecture, flip-flops, integrated circuit design, logic design, microprocessors.  ...  ACKNOWLEDGMENT The microprocessors described in this paper have resulted from the work of a tremendous number of people.  ... 
doi:10.1109/4.668981 fatcat:572fe6sfifb7zg7za4bqesizii

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

Dongwan Ha, Kyoungho Woo, Scott Meninger, Thucydides Xanthopoulos, Ethan Crain, Donhee Ham
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Microprocessor thermal profiling can be a potential application.  ...  After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 m fall within C in a temperature range of C, where the temperature chamber used has a control uncertainty of C.  ...  Cole of Cambridge University for their suggestions, and A. Jain of Cavium Networks for support.  ... 
doi:10.1109/tvlsi.2011.2161783 fatcat:oc342lwsyffote5d4wvjspg4ua
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