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A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin
2017 IEICE Electronics Express  
A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter.  ...  A TSPC dual-modulus prescaler is proposed to reduce the PLL's power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops.  ...  With the improved speed of the MOS devices, in several GHz applications, the current-mode-logic (CML) divider can be replaced with the true single-phase clocked (TSPC) logic to reduce the power consumption  ... 
doi:10.1587/elex.14.20170065 fatcat:flwtc6va4zgcvdulkp7buqcjja

A 2-to-2.4-GHz differentially-tuned fractional-Nfrequency synthesizer for DVB tuner applications

Meng Lingbu, Lu Lei, Zhao Wei, Tang Zhangwen
2010 Journal of Semiconductors  
Test results show that the RMS phase error is less than 0.7 ı in integer-N mode and less than 1 ı in fractional-N mode.  ...  This paper describes the design of a fractional-N frequency synthesizer for digital video broadcastingterrestrial (DVB-T) receivers.  ...  Fig. 3 . 3 PLL locking time simulation. Fig. 4 . 4 PLL phase noise simulation. Fig. 5 . 5 Block diagram of the 2-2.4 GHz fractional-N frequency synthesizer.  ... 
doi:10.1088/1674-4926/31/7/075007 fatcat:fxrj5errgzcenig5gpxardm7ba

A 12GHz programmable fractional-n frequency divider with 0.18um CMOS technology

Siavash Heydarzadeh, Pooya Torkzadeh, Mohammad Pourmina
2013 2013 5th Computer Science and Electronic Engineering Conference (CEEC)  
In this paper, the design of fractional-n (n: 2, 3, ..., 8) extended True-Single-Phase-Clock (E-TSPC) frequency dividers with 0.18µ CMOS technology and TSMC process is presented.  ...  The E-TSPC circuits have a small area occupation, extremely low power consumption (less than 220µW from 1.8V supply voltage) and 50% duty-cycle sinusoidal output voltage.  ...  In PLL synthesizer, frequency True-Single-Phase-Clock (E-TSPC) FFs for high-speed divider is the most significant parts that consumes a large and low power consumption components.  ... 
doi:10.1109/ceec.2013.6659440 fatcat:dvobncns75fuphhu5csj2xmgvm

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

Bing Hou, Hua Chen, Zhiyu Wang, Jiongjiong Mo, Junli Chen, Faxin Yu, Wenbo Wang
2017 Sensors  
The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity  ...  In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed.  ...  However, it is quite power consuming compared with dynamic digital logic such as true-single-phase-clock (TSPC).  ... 
doi:10.3390/s17020223 pmid:28125033 pmcid:PMC5335926 fatcat:fk2elyo7nnc33a63oy2qjebw5a

A 1-V 600μA CMOS Fractional-N Synthesizer with External Inductor QVCO for Med Radio Receiver

Dan Yan
2012 International Journal of Information and Electronics Engineering  
ACKNOWLEDGEMENTS The authors would like to thanks for the assistance of the staff of Integrated Circuits and Systems Laboratory at the Institute of Microelectronics, A*Star, Singapore, in the successful  ...  Prescaler, Counters and 3rd-Order MASH Σ-Δ Modulator A true-single-phase clock (TSPC) prescaler 8/9 is used for the synthesizer [9] .  ...  Design, implementation and measurement results of medradio fraction-N synthesizer have been presented. The chip consumes 600uA from a single 1V power supply achieving -106dBc/HZ at 100KHz offset.  ... 
doi:10.7763/ijiee.2012.v2.230 fatcat:klasqgbf2jgljct456re43vxzy

77 GHz waveform generator with multiple frequency shift keying modulation for multi-target detection automotive radar applications

Quang Nguyen, Franklin Bien, Youngsu Kim, Myungryeol Park
2015 Electronics Letters  
This waveform shows good performance, with a high range and velocity resolution, short measurement time, and ability to avoid ghost targets. The main drawback of this modulation is the complexity.  ...  D flip-flop is a modification of the True Single-Phase Clock (TSPC) flipflop, as shown in Figure 3.2-b.  ...  The fractional-N PLL operates at 12.65-12.85 GHz to ease the circuit design. Thus, a frequency multiplier is needed.  ... 
doi:10.1049/el.2015.0092 fatcat:dggivhke7fggfnumwkakge736y

A 2-V CMOS cellular transceiver front-end

M.S.J. Steyaert, J. Janssens, B. de Muer, M. Borremans, N. Itoh
2000 IEEE Journal of Solid-State Circuits  
The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked  ...  A/D, D/A, and the all-digital delta-sigma fractional-PLL steering.  ...  The high-speed division of the prescaler is done with two dynamic single transistor clocked logic (DSTC) n-latches [5] , forming a differential dynamic D-flip-flop, which is clocked by the differential  ... 
doi:10.1109/4.890303 fatcat:zehxbpys3zbuzo36l57pvgunt4

FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL

Sung Tae Moon, Ari Yakov Valero-López, Edgar Sánchez-Sinencio
2005 International Journal of High Speed Electronics and Systems  
Frequency synthesizer is a key building block of fully-integrated wireless communications systems.  ...  Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.  ...  Keliu Shu, at Texas Instrument; and Alberto Valdes-Garcia, at Texas A&M University, for their invaluable contributions in the form of technical discussions.  ... 
doi:10.1142/s0129156405003235 fatcat:lma5m4s6bvhpzklsn4hpmobzsy

FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL [chapter]

Sung Tae Moon, Ari Yakov Valero-López, Edgar Sánchez-Sinencio
2006 Design of High-Speed Communication Circuits  
Frequency synthesizer is a key building block of fully-integrated wireless communications systems.  ...  Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.  ...  Keliu Shu, at Texas Instrument; and Alberto Valdes-Garcia, at Texas A&M University, for their invaluable contributions in the form of technical discussions.  ... 
doi:10.1142/9789812774583_0005 fatcat:ug22esmsgbax5gqaqbmfqtb7fy

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

Jri Lee, Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang
2010 IEEE Journal of Solid-State Circuits  
Index Terms-77 GHz, fast Fourier transform (FFT), fractional-synthesizer, frequency modulated continuous-wave (FMCW) radar, low-noise amplifier (LNA), power amplifier (PA).  ...  A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed.  ...  The on-chip 2 CML and true-single-phase clock (TSPC). transmission line design is not trivial at such a high frequency.  ... 
doi:10.1109/jssc.2010.2075250 fatcat:fxjdpdej6vbrba6qf5dlxzqrwe

Digitally-Compensated Wideband 60 GHz Test-Bed for Power Amplifier Predistortion Experiments

Martin Pospíšil, Roman Maršálek, Tomáš Götthans, Tomáš Urbanec
2021 Sensors  
It also demonstrates the potential of digital predistortion linearization on two distinct 60 GHz power amplifiers: one integrated in a direct-conversion transceiver and an external one with 24 dBm output  ...  and equipped with digital compensation for the most critical front-end impairments, including the digital predistortion of the power amplifier.  ...  The sampling clock source is the ultra-low-phase-noise SAW (Surface Acoustic Wave) oscillator Crystek CCSO-914X3 (1 GHz) with a sinusoidal output.  ... 
doi:10.3390/s21041473 pmid:33672523 fatcat:ieiuo4yx2rabdmvfifu2r5zpka

A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure

Saleh Abdel-Hafeez, Ann Gordon-Ross
2011 Circuits, systems, and signal processing  
We implemented our proposed divider using a 0.15-µm TSMC digital cell library and achieved a maximum operating frequency of 2 GHz, an area of 112 848 µm 2 (900 transistors), and consumed 15.47 mW of power  ...  We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits.  ...  The power consumption of [26] measured at 2 GHz is the least power consumption of the compared designs due to the use of extended true-single-phase-clock for flip-flop components [13] .  ... 
doi:10.1007/s00034-011-9279-8 fatcat:2znob4ekzveotfzhs2lfjyhwfm

PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops [chapter]

Marina de Queiroz Tavares
2000 Analog Circuit Design  
They consist of a tunable oscillator and a programmable phase controlling loop. Current tendencies in PLL development focus noise performance and a higher integration level.  ...  A top-down system to circuit approach, studies noise generation and transmission. Finally testchip realizations of PLLs with fully gm-C integrated oscillators are presented.  ...  TC3 : single PLL plus QCCO circuit The testchip TC3 contains a low noise satellite PLL plus a QCCO.  ... 
doi:10.1007/978-1-4757-3198-9_17 fatcat:tc4trqyzcve2dfj57xif7dgmka

Phase meter based on zero-crossing counting of digitized signals [article]

Wataru Kokuyama, Hideaki Nozato, Thomas R. Schibli
2020 arXiv   pre-print
Low-noise differential phase measurements can be done for square waves (-204 dBrad^2/Hz for a 1-kHz, 1-V_p-p signal, 10 Hz-1 kHz offset, with cross-correlation) as well as sinusoidal waves, with a measurement  ...  We developed a compact and easy-to-use phase meter based on a zero-crossing counting algorithm for digitized signals. Owing to the algorithm, the phase meter has low-noise and wide dynamic range.  ...  error behaves when the true phase moves over a single cycle (0 rad to 2 rad), instead of the phase error itself.  ... 
arXiv:2009.01137v2 fatcat:oh5v47qamjaqzbw2yhf2zueo2m

DESIGN AND SIMULATION OF 2.4GHz CMOS FREQUENCY SYNTHESIZER FOR S BAND APPLICATION

S Shah, A Suthar
2016 unpublished
With the increasing demand for low cost and high performance of wireless transceiver building blocks, the low-power requirement is a great concern for radio-frequency integrated circuit (RFIC) designers  ...  The objective of this research work is to design this critical blocks for the frequency synthesizer with low power requirement.  ...  A. K. Sisodia & Asst. Prof. Ami M. Patel. from L. J. Institute of Engineering and Technology for technical discussion & processing support without whom this paper would never be completed.  ... 
fatcat:3iae4x5jefasdahwksggymyglu
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