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An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding

Jianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, Xiexiong Chen
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
This paper proposes an efficient SIMD architecture with parallel memory for 2D cosine transforms of multiple video standards.  ...  The simulation results show that proposed architecture achieves significant performance improvement with low hardware cost of 3.2K equivalent gate count for parallel memory subsystem (not including SRAMs  ...  We propose 4 novel instructions fRTRAN, fCTRAN, iRTRAN and iCTRAN to efficiently execute the forward/inverse transform. Each instruction performs the operations of Fig.8 (a-d) .  ... 
doi:10.1109/asap.2007.4429990 dblp:conf/asap/PengQLYC07 fatcat:dyjkejsewvcl7naoyl63oxbh54

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa
2011 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4 × 4 / 2 × 2 Hadamard transforms.  ...  An innovative high throughput and scalable multitransform architecture for H.264/AVC is presented in this paper.  ...  Such processing structure makes use of a 2-D array of PEs and of a memory free transpose circuit to realize the H.264/AVC 2-D 4 × 4 forward/inverse integer DCT and the 4×4 / 2×2 Hadamard transforms, by  ... 
doi:10.1109/samos.2011.6045465 dblp:conf/samos/DiasLRS11 fatcat:kqpxrpfvrjdxrmqozytpusbeya

Adaptive Low-Power Architectures for Embedded Multimedia Systems [chapter]

Muhammad Shafique, Jörg Henkel
2011 Hardware/Software Architectures for Low-Power Embedded Multimedia Systems  
study of H.264/AVC video codec.  ...  The goal of high-performance is achieved by exploiting the potential of area, power reduction and throughput enhancement at the algorithm design as well as at the processor architecture levels without  ...  and forward/inverse integer transform units in H.264/AVC foe a reconfigurable VLIW processor.  ... 
doi:10.1007/978-1-4419-9692-3_3 fatcat:hfcxk5zklfdodffl4hwvgurz6u

Hardware architecture design of an H.264/AVC video codec

Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required.  ...  This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed.  ...  In [16] , the forward/inverse multi-transform are designed to support 4×4 DCT, IDCT, and Hadamard transforms.  ... 
doi:10.1145/1118299.1118473 fatcat:i7xscbbjvbew3jlmjda3cwhqky

High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC

Tiago Dias, Luis Rosario, Nuno Roma, Leonel Sousa
2012 2012 15th Euromicro Conference on Digital System Design  
This architecture is based on a highly flexible processing structure that is suitable for very efficient implementations using both FPGA and ASIC technologies.  ...  A new high-performance and reduced hardware architecture for the computation of the H.264/AVC forward and inverse quantization operations is presented in this paper.  ...  Nonetheless, most known proposals of quantization circuits for H.264/AVC are still based on generic multipliers.  ... 
doi:10.1109/dsd.2012.73 dblp:conf/dsd/DiasRRS12 fatcat:ugwrv3k4i5hm3cgxhmpoj7hh2m

Algorithm analysis and architecture design for HDTV applications

Tung-Chien Chen, Hung-Chi Fang, Chung-Jr Lian, Chen-Han Tsai, Yu-Wen Huang, To-Wei Chen, Ching-Yeh Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
2006 IEEE Circuits & Devices  
H.264 Overview H.264/AVC can save 25-45% and 50-70% of bit rates compared with MPEG-4 advanced simple profile (ASP) and MPEG-2, respectively [1].  ...  Furthermore, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are too constrained  ...  Therefore, engines of intraprediction together with forward/inverse transform/quantization are located in the same IP stage.  ... 
doi:10.1109/mcd.2006.1657846 fatcat:w7ir2pibtzh4vjv54i26co7raa

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Liang-Gee Chen
2006 IEEE transactions on circuits and systems for video technology (Print)  
On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional  ...  In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained  ...  The iprof [15] , a software analyzer on the instruction level, is used to profile an H.264/AVC encoder on a processor-based platform (SunBlade 2000 workstation, 1.015 GHz Ultra Sparc II CPU, 8 GB RAM,  ... 
doi:10.1109/tcsvt.2006.873163 fatcat:xkacmieygfabtnysizpqozmeva

Power-aware HEVC decoding with tunable image quality

Erwan Nogues, Simon Holmbacka, Maxime Pelcat, Daniel Menard, Johan Lilius
2014 2014 IEEE Workshop on Signal Processing Systems (SiPS)  
Among those, the emerging High Efficiency Video Coding (HEVC) provides a better video quality for the same bit rate than the previous H.264 standard.  ...  Our experiments reveal that the modified HEVC video decoder can save up to 28 % of power consumption in real-world platforms while keeping better quality than decoding with H.264.  ...  The pair of forward-inverse transforms can be pre-calculated and merged for fractional position [12] .  ... 
doi:10.1109/sips.2014.6986059 dblp:conf/sips/NoguesHPML14 fatcat:ppdrgnpwh5bnbmacr52cl766ma

Hardware architecture design of an H.264/AVC video codec

Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
Asia and South Pacific Conference on Design Automation, 2006.  
Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required.  ...  This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed.  ...  In [16] , the forward/inverse multi-transform are designed to support 4×4 DCT, IDCT, and Hadamard transforms.  ... 
doi:10.1109/aspdac.2006.1594776 dblp:conf/aspdac/ChenLC06 fatcat:bl4y2cbqobfebkm7q762d4baji

Analysis and Architecture Design of an HDTV720p30 Frames/s H.264/AVC Encoder

Priyanka Bhagwat
2016 unpublished
On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional  ...  In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained  ...  Six kinds of 2-D transform, 4 4/2 2 DCT/IDCT/Hadamard transform, are involved in reconstruction loops.  ... 
fatcat:g3st4pcf4fesdkom6f4fvifmzq

Perceptual coding of digital audio

T. Painter, A. Spanias
2000 Proceedings of the IEEE  
Next, filter bank design issues and algorithms are addressed, with a particular emphasis placed on the modified discrete cosine transform, a perfect reconstruction cosine-modulated filter bank that has  ...  These discussions concentrate on architectures and applications of those techniques that utilize psychoacoustic models to exploit efficiently masking characteristics of the human receiver.  ...  The forward/inverse transform matrices of a particular wavelet are associated with a corresponding QMF analysis/synthesis filter bank.  ... 
doi:10.1109/5.842996 fatcat:jkfvoxg7zrcyxg6fyahe4u73pu

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

Marcelo Brandalero, Antonio Carlos Beck
2019 Anais Estendidos do Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD)   unpublished
Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3×, or adapt to the same task deadline with 1:6× smaller  ...  The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation.  ...  H.264 Source: (MITTAL, 2016).  ... 
doi:10.5753/wscad_estendido.2019.8706 fatcat:4wkgxmshlzgnno55wpw45dtamq