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Session 28 Overview: DRAM and Interface
2022
2022 IEEE International Solid- State Circuits Conference (ISSCC)
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New design features include an in-DRAM ECC, internal NN-DFE, TSV auto-calibration, and machine-learning driven layout optimization. ...
In Paper 28.1, SK Hynix presents a 12-high stack, 192Gb HBM3 with a 7Gb/s/pin I/O speed to reach a 896GB/s bandwidth. ...
Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process Dae-Hyun Kim, Samsung Electronics, Hwaseong, Korea In Paper 28.3, Samsung presents a 16Gb LPDDR5X SDRAM ...
doi:10.1109/isscc42614.2022.9731539
fatcat:nhhntu77kjhojjyjnuoqzobqgi