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An ultra-compact and low-power oven- controlled crystal oscillator design for precision timing applications

Jaehyun Lim, Hyunsoo Kim, T N Jackson, Kyusun Choi, D Kenny
2010 IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control  
a large package size and a long warm-up time.  ...  However, a typical OCXO package includes not only a metal block, but also multiple PCBs for the resonator, oscillator circuitry, and temperature sensitive components, the combination of which results in  ...  MOSIS Parametric Test Results for AMIS 0.5 μm CMOS Run ........................101 Appendix B MOSIS Parametric Test Results for TSMC 0.35 μm CMOS Run .....................107 Appendix C MOSIS Parametric  ... 
doi:10.1109/tuffc.2010.1638 pmid:20875980 fatcat:yuho5fwwzveffppt73cy2renuu

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes [article]

Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank Gurkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
2020 arXiv   pre-print
This work presents Arnold: a 0.5 V to 0.8 V, 46.83 uW/MHz, 600 MOPS fully programmable RISC-V Microcontroller unit (MCU) fabricated in 22 nm Globalfoundries GF22FDX (GF22FDX) technology, coupled with a  ...  A unique feature of the proposed SoC is the exploitation of body-biasing to reduce leakage power of the embedded FPGA (eFPGA) fabric by up to 18x at 0.5 V, achieving SoA state bitstream-retentive sleep  ...  voltage and frequency scalable architecture from 0.5 V to 0.8 V, with a peak energy efficiency of 46.83 µW/MHz at 0.52 V and a maximum frequency of 600 MHz at 0.8 V.  ... 
arXiv:2006.14256v1 fatcat:e7zuiqpiinesjco4t6cizhklya

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Mile Stojcev, Teufik Tokic, Ivan Milentijevic
2004 Facta universitatis - series Electronics and Energetics  
This paper overviews some of the microarchitectural techniques that are typical for contemporary high-performance microprocessors.  ...  In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance.  ...  (MHz) 750 1200 1400 1600 2000 2500 3000 Local clock freq. (MHz) 750 1250 1500 2100 3500 6000 10000 Maximum power/chip (W) 70 90 110 130 160 170 175  ... 
doi:10.2298/fuee0403285s fatcat:gaxelp2aebbnvinhxssaydxhvy

A 200 MHz 32 b 0.5 W CMOS RISC microprocessor

R. Stephany, K. Anne, J. Bell, G. Cheney, J. Eno, G. Hoeppner, G. Joe, R. Kaye, J. Lear, T. Litch, J. Meyer, J. Montanaro (+7 others)
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)  
This paper describes a 160 MHz 500 mW StrongARM microprocessor designed for lowpower, low-cost applications.  ...  At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW.  ...  He was a senior hardware engineer in Digital's Palo Alto Design Center, where he led the bus interface unit design for the StrongARM SA-110 microprocessor chip.  ... 
doi:10.1109/isscc.1998.672451 fatcat:rrrpqs4xvbcurlh4l7vpmfs3ha

A review of advances in pixel detectors for experiments with high rate and radiation

Maurice Garcia-Sciveres, Norbert Wermes
2018 Reports on progress in physics (Print)  
p-well (C W W ) play a significant role.  ...  Such large changes will limit the achievable clock speed, but most pixel ROIC applications require clocks of order 100 MHz, rather than the typical GHz speeds of microprocessors in the same technology.  ... 
doi:10.1088/1361-6633/aab064 pmid:29457774 fatcat:ef6x6jxhbvarnkpqqcwuxj3nda

Neuromorphic microelectronics from devices to hardware systems and applications

Alexandre Schmid
2016 Nonlinear Theory and Its Applications IEICE  
A regain of interest has been observed in the middle of the 2010s', which manifests itself from the emergence of large-scale projects integrating various computational and hardware perspectives, by the  ...  One architectural SpiNNaker node consists of 18, 200 MHz, 32-bit ARM9 processors, each with 96 kB of local memory, 128 MB of shared memory, a dedicated packet router, as well as peripheral support hardware  ...  , a 32-bit adder, and a shifting unit aside two 16-bit busses.  ... 
doi:10.1587/nolta.7.468 fatcat:2lvkjxhetnghtmbbow4mfcqqjm

A Batteryless 19 $\mu$W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications

Yanqing Zhang, Fan Zhang, Yousef Shakhsheer, Jason D. Silver, Alicia Klinefelter, Manohar Nagaraju, James Boley, Jagdish Pandey, Aatmesh Shrivastava, Eric J. Carlson, Austin Wood, Benton H. Calhoun (+1 others)
2013 IEEE Journal of Solid-State Circuits  
This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and transmitting electrocardiogram  ...  The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming 19 W, running solely on harvested energy.  ...  The zoomed-in section shows one 44 b packet of data, including 9 b header, 32 b data, and 3 b CRC.  ... 
doi:10.1109/jssc.2012.2221217 fatcat:dhzv7r5vcbhxxlxb4lq2t7j6ya

Power and energy efficiency evaluation for HW and SW implementation of nxn matrix multiplication on Altera FPGAs

Abdelghani Renbi, Lennart Lindh
2009 Proceedings of the 6th FPGAworld Conference on - FPGAworld '09  
Low power design has traced a new era.  ...  simple RISC processor.  ...  a throughput W.  ... 
doi:10.1145/1667520.1667526 fatcat:rgt4z4f75zgfda5n55m6lv2bqm

An Energy and Performance Exploration of Network-on-Chip Architectures

A. Banerjee, P.T. Wolkotte, R.D. Mullins, S.W. Moore, G.J.M. Smit
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power.  ...  In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately  ...  The power is measured for a 0.13-m CMOS technology, nominal process operating at 1.2 V, 25 C and a data path of 32-bits.  ... 
doi:10.1109/tvlsi.2008.2011232 fatcat:5vm7mpsl3zhd3apbh36xocbk3i

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede
2008 2008 IEEE International SOC Conference  
Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.  ...  Modeling and Simulation 0 20 40 60 80 100 120 140 160 IDLE BUSY A BUSY B BUSY C MAC MICROPROCESSOR 0 20 40 60 80 100 120 140 160 IDLE BUSY A BUSY B BUSY C TASK HANDLER FOR  ...  It is fabricated on 0.13 micron CMOS. It provides Dual 60 MHz RISC processors, one for MAC and one for PHY, and accelerators for Encryption and other MAC functions.  ... 
doi:10.1109/socc.2008.4641500 dblp:conf/socc/NabiWV08 fatcat:nxa65gzgxvewnlhhaqnozy6lfu

Architectural Enhancements for Color Image and Video Processing on Embedded Systems [chapter]

Jongmyon Kim, D. Scott Wills, Linda M. Wills
2005 Lecture Notes in Computer Science  
(b) A packed max instruction. Figure 31 . 31 Figure 31. (a) A rotate instruction. (b) A mix instruction. Figure 32 . 32 Figure 32. An absolute-differences-accumulate instruction.  ...  (b) A packed max instruction. Figure 31 . 31 Figure 31. (a) A rotate instruction. (b) A mix instruction. Figure 32 . 32 Figure 32. An absolute-differences-accumulate instruction.  ... 
doi:10.1007/11572961_10 fatcat:akghmv4vajhnhksbm4osyq6u2i

Modular vector processor architecture targeting at data-level parallelism

Seyed A. Rooholamin, Sotirios G. Ziavras
2015 Microprocessors and microsystems  
For example, it achieves a larger than 1500-fold speedup in the color space converting benchmark compared to running the code on a scalar core.  ...  Compared to running the benchmark on a VP without the shuffle engines, the speedup is 5.92 and 7.33 for the 64-point FFT without and with compiler optimization, respectively.  ...  The MB soft core is a 32-bit RISC Harvard architecture that supports the AXI4 and LMB (Local Memory Bus bus interfaces.  ... 
doi:10.1016/j.micpro.2015.04.007 fatcat:n2h2nbsvtjeu5dnor4lea625qq

FPGA Architecture: Survey and Challenges

Ian Kuon, Russell Tessier, Jonathan Rose
2007 Foundations and Trends® in Electronic Design Automation  
There are a number of programming technologies and their differences have a significant effect on programmable logic architecture.  ...  We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.  ...  W ire A W ire B W ire C W ire D W ire A W ire B W ire C W ire D (a) (b) Circuit-Level Techniques to Improve Routing Several researchers have attempted to improve the performance of interconnect wires  ... 
doi:10.1561/1000000005 fatcat:ebex55milfgczim2i4wi2apbqy

Radiation Tolerant Electronics

Paul Leroux
2019 Electronics  
At the end of the experiment [500 krad(Si)], the average RO frequencies of FPGA1 and FPGA2 have decreased to 195.1 MHz (0.5%) and 197.92 MHz (0.6%) respectively.  ...  This SoC is divided into two parts, an FPGA area (programmable logic-PL) and a 32-bit ARM cortex A9 microprocessor (processing system-PS).  ...  Microprocessors, for example, are widely used in the image processing field, so soft errors in some critical parts of the processor such as the program counter register can cause unexpected crashes or  ... 
doi:10.3390/electronics8070730 fatcat:wjo5prr5xjeqtlhxlj4kqz5st4

Floating-Point Fused Multiply-Add Architectures

Eric Quinnell, Earl E. Swartzlander, Carl Lemonds
2007 Asilomar Conference on Signals, Systems and Computers. Conference Record  
i i i i g g z z t g z z g t f b a z b a g b a t + + = = = + = = i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i t w x s neg f x w e w t e pos f c b a b a x c b a w c b a t c  ...  b a c b a e c b a s A Fused Multiplier-Adder with Floating-Point Adder Bypass The final paper included in this section is a second paper by Lang and Bruguera [32] .  ...  The new architecture's parallelism is not an attempt to force a fused multiply-add into a floating-point adder dual-path system, as suggested by previous works.  ... 
doi:10.1109/acssc.2007.4487224 fatcat:ug5id44hqfeenc3sppzrhoxsuy
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