A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Filters
A 12-bit 40-MS/s SAR ADC with Calibration-Less Switched Capacitive Reference Driver
2020
Electronics
Preserved Fulltext
To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. ...
With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about a 16 dB improvement from the SFDR of a SAR ADC with a CRD only. ...
Figure 7 . 7 DNL and INL of a behavioral simulation for a 12-bit SAR ADC according to and the RSC. ...
doi:10.3390/electronics9111854
fatcat:flex2gsqqvbxnexsanqb5momfu
A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System
2022
Micromachines
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced ...
In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital ...
In addition, a 12 bit 40 MS/s SAR ADC (as shown in Figure 4b ) realized fast-binary-window (FBW) DAC switching technology was proposed by Chung et al. [36] . ...
doi:10.3390/mi13010114
pmid:35056279
pmcid:PMC8779678
fatcat:nxirhfhgzjcvlojql2k6sflxfi
2020 Index IEEE Journal of Solid-State Circuits Vol. 55
2020
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
., see Zhao, B., JSSC Feb. 2020 249-260 Iotti, L., Krishnamurthy, S., LaCaille, G., and Niknejad, A.M., A Low-Power 70-100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback; JSSC Aug. 2020 ...
2043-2054 Ishigaki, Y., see Yamada, Y., JSSC Jan. 2020 120-132 Ishii, H., see Kondo, S., 2866-2877 Isobe, A., see Furubayashi, Y., 2539-2552 Itami, G., see Hamada, H., 2316-2335 Ito, M., see Kondo ...
., +, JSSC Feb. 2020 312-321 A 13-bit 0.005-mm 2 40-MS/s SAR ADC With kT/C Noise Cancellation. ...
doi:10.1109/jssc.2021.3054535
fatcat:rfm7shuowvakfgzumgtqzlod5i
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology
2015
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
SUMMARY An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. ...
As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration. ...
In [14] , the characteristic of a 40 MS/s TAD has been experimentally confirmed in a wide range of temperature from −40 • C to 125 • C. ...
doi:10.1587/transfun.e98.a.466
fatcat:fs7ntb3c45ex5i2weqsz65ygui
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
., +, TVLSI Oct. 2018 1967-1979
A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching
Scheme. ...
., +, TVLSI Oct. 2018 1967-1979
A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching
Scheme. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65
2018
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
., +,
TCSI Aug. 2018 2631-2640
A 12-b 40-MS/s Calibration-Free SAR ADC. ...
Li, B., +, TCSI July 2018 2169-2182
A 12-b 40-MS/s Calibration-Free SAR ADC. Hsu, C., +, TCSI March
2018 881-890
A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Record-
ing Systems. ...
doi:10.1109/tcsi.2019.2896877
fatcat:3lzpngw2ofdjhiculf7ehrjeam
Software-Defined Radio Front Ends
[chapter]
2010
Multi-Mode/Multi-Band RF Transceivers for Wireless Communications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
In the link budget used here, typically 8 to 10 bits are needed with sampling speeds up to 40 MS/s (two of them should be interleaved to achieve 80-MS/s operation for 802.11n systems). ...
This feature makes the
FIGURE 1 . 1 14 Charge-sharing SAR ADC: (a) basic architecture; (b) sample waveforms. ...
doi:10.1002/9780470634455.ch1
fatcat:aqp226s3jbghfdlmjc564ymopy
Design Techniques for Analog-to-Digital Converters in Scaled CMOS Technologies
2017
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
CRP techniques are specifically applied to Zero-Crossing Based (ZCB) Pipeline-SAR ADCs in this work. ...
The next prototype describes the design of a radiation-hard dual-channel 12-bit 40MS/s pipeline ADC with extended dynamic range, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters ...
Calibration improves the spurious-free dynamic range (SFDR) from 52.7 dB to 77.8 dB while the signal-to-noise and distortion ratio (SNDR) improves from 49.INL/DNL at 40 MS/s (Chip 1): (left) before calibration ...
doi:10.7916/d8rv0kt8
fatcat:rks4j2zjfvctfbwqxaamkavvgu
A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter
2020
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
An automatic calibration procedure has been developed to optimized the configuration settings for the chip. ...
To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics requires a low-power monolithic solution. ...
The speed can be much faster to reach 40 Ms/s at 10-bit resolution in the 0.13 µm CMOS technology [83, 84] , which is the common-used technology node in nuclear electronics. ...
doi:10.11588/heidok.00028659
fatcat:2t4xijsz45clzeffdaocclygdi
nEXO Pre-Conceptual Design Report
[article]
2018
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Other Versions
This design for nEXO presents a compelling path towards a next generation search for 0νββ, with a substantial possibility to discover physics beyond the Standard Model. ...
The sensitivity increase is, therefore, entirely derived from the increase of active mass in a monolithic and homogeneous detector, along with some technical advances perfected in the course of a dedicated ...
In this case, four front end channels share one 8 MS/s, 12-bit SAR (successive approximation register) ADC in fully differential mode. ...
arXiv:1805.11142v2
fatcat:jybtd2buizckjmhbqwparohlve