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Adnan Gundel, Scott Jorek, Pawel Janczykowski, Al Trezza, Richard Goldblatt
2006 2006 IEEE Long Island Systems, Applications and Technology Conference  
Implemented in a standard 0.35-μm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets  ...  ABSTRACT LOW JITTER PHASE-LOCKED LOOP CLOCK SYNTHESIS WITH WIDE LOCKING RANGE by A d n a n G ϋ n d e l The fast growing demand of wireless and high speed data communications has driven efforts to increase  ...  It consists of a simple combinational logic circuit, a diode connected transistor M1, which creates a gate voltage to turn on M2 to pull down the inputs of several logic gates to ground.  ... 
doi:10.1109/lisat.2006.4302658 fatcat:l2646fpu4jdqveddl23wnlrtpu

The circuit and physical design of the POWER4 microprocessor

J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, C. J. Anderson
2002 IBM Journal of Research and Development  
The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz.  ...  Contracts are the early size and timing budgets IBM Abstract Netlists Spice Noise rule Layout Custom macros Reports  ...  Acknowledgments The authors wish to acknowledge all of our colleagues on the POWER4 design team, as well as many others in IBM who have contributed to the POWER4 design.  ... 
doi:10.1147/rd.461.0027 fatcat:wp4ojp7zyfam5nhtajbfdfh2uy

A 100 MHz PRF IR-UWB CMOS Transceiver With Pulse Shaping Capabilities and Peak Voltage Detector

Remy Vauche, Eloi Muhr, Olivier Fourquin, Sylvain Bourdel, Jean Gaubert, Nicolas Dehaese, Stephane Meillere, Herve Barthelemy, Laurent Ouvry
2017 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
It uses standard CMOS logic gates as buffers, transmission gates, and an OR gate.  ...  Abstract-This work presents a high rate IR-UWB transceiver chipset implemented in a 130 nm CMOS technology for WBAN and biomedical applications in the 3.1GHz-4.9GHz band.  ... 
doi:10.1109/tcsi.2017.2669902 fatcat:kuvb37elgbdlnkuvtnij3wslfq

Understanding Smart Sensors

Randy Frank
2000 Measurement science and technology  
ASIC technology consists of programmable logic devices (PLDs) for low-circuit density (<5,000 gates), gate arrays for medium density (<100,000 gates), and standard cells for high-end custom circuits.  ...  Control Techniques State Machines The state machine is one of the most commonly implemented functions in programmable logic [7] . The state machine is actually a sequencing algorithm.  ...  bridge device that forwards packets of information between channels in a multiple-media network broadband a modulated or square wave signal on a multiple modulated carrier bulk micromachining a process  ... 
doi:10.1088/0957-0233/11/12/711 fatcat:inet5t3lzbecrczd2f5tdevkzq

Physical Fault Injection and Side-Channel Attacks on Mobile Devices: A Comprehensive Analysis [article]

Carlton Shepherd, Konstantinos Markantonakis, Nico van Heijningen, Driss Aboulkassimi, Clément Gaine, Thibaut Heckmann, David Naccache
2021 arXiv   pre-print
Today's mobile devices contain densely packaged system-on-chips (SoCs) with multi-core, high-frequency CPUs and complex pipelines.  ...  In this survey, we consolidate recent developments in physical fault injections and side-channel attacks on modern mobile devices.  ...  Acknowledgements Funding: This work received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No. 88315 (EXFILES).  ... 
arXiv:2105.04454v5 fatcat:27ldfag7ejgvxh7cbs2qnevb24

Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers [chapter]

2009 Phase-Locking in High-Performance Systems  
For each block, the phase noise or jitter is extracted and applied to a model for the entire PLL.  ...  The methodologies begin by characterizing the noise behavior of the blocks that make up the PLL using transistor-level RF simulation.  ...  The noise of OSC is -95 dBc/Hz at 100 kHz. Applying (86) to compute c, where L(Δf ) = 316 × 10 -12 , Δf = 100 kHz, and f o = 25 MHz, gives c = 5 × 10 -15 .  ... 
doi:10.1109/9780470545492.ch5 fatcat:nqidim2yb5gpbplhf3ovpifyfq

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
i This page intentionally left blank. ii FOREWORD This document reflects the thoughts of a group of highly talented individuals from universities, industry, and research labs on what might be the challenges  ...  in advancing computing by a thousandfold by 2015.  ...  A goal of Chapel is to provide better abstractions for separating algorithmic logic and data structure implementation and to provide programmers with a global view of the computation, rather than programming  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m

Future trends in microelectronics - reflections on the road to nanotechnology

1997 Precision engineering  
(100k gates/chip and above) levels of integration.  ...  Switched DC Logic Implementations Conventional CMOS logic can be considered to be a complex network of voltage controlled switches (transistors) which establish a '0' or '1' logic level by switching a  ...  The key to a successful implementation of an all-optical PLL is our recent breakthrough in the conceptualization and experimental demonstration of a laser mixer which manipulates the microwave envelopes  ... 
doi:10.1016/0141-6359(97)90048-9 fatcat:j7blw4wn6zbitmoqqffj46g54e

Bandpass Delta-Sigma Converters in IF Receivers [chapter]

Armond Hairapetian
2001 Analog Circuit Design  
on board.  ...  Back cover: The four squares on the back side of the thesis, symbolize the categories in which this thesis is split to analyze the quality of a system.  ...  MHz] |A| [dB] |A| [dB] f [MHz] 0 -40 -60 -100 -140 -6 6 0 -20 -80 -120 0 -40 -60 -100 -140 -30 30 0 -20 -80 -120 frequency [MHz] |A| [dB] |A| [dB] frequency  ... 
doi:10.1007/978-1-4613-1443-1_10 fatcat:cg34vk7z65cgleckvjw5lbhiqe

Circuits, Architectures and Antenna Design For 5G Wireless Transceivers

Waleed M. El-Halwagy
For enhanced performance, the cascaded PLL is then proposed which consumes 26.9-mW and achieves less than 100-fs jitter with -112.6-dBc/Hz phase noise at 1-MHz offset in the fractional-N mode.  ...  First, the single-stage PLL is presented which ABSTRACT iii consumes 35.8-mW while achieving 500-fs jitter.  ...  gratitude to the entire institution of the Electrical and Computer Engineering (ECE) department at the University of Alberta for all the support they give to the graduate students to help them focus on  ... 
doi:10.7939/r36h4d56h fatcat:xaikovsakjc7lnytf5cgazwd4y

Analysis and Mitigation of Remote Side-Channel and Fault Attacks on the Electrical Level

Jonas Krautter, Mehdi B. Tahoori, Thomas Eisenbarth
programmable logic device s713 ISCAS'85/'89 based on programmable logic device s820 ISCAS'85/'89 resynthesized s832 without redundancies s832 ISCAS'85/'89 based on programmable logic device s838_1 ISCAS  ...  We are able to create Design Collection Description #LEs s27 ISCAS'85/'89 unknown s208_1 ISCAS'85/'89 based on programmable logic device s298 ISCAS'85/'89 based on programmable logic device s344 ISCAS'  ...  A.1.5. NOP Code Pattern . r e p t 3000 mov r4 , r 4 . endr A.2.  ... 
doi:10.5445/ir/1000144660 fatcat:kth32c56kzfmzlblmhp75pprju

Self-Cascode Structures Using Optional devices in Standard CMOS Technology 스마트 보안 시스템을 위한 가변해상도 픽셀 기법의 CMOS 이미지 센서 설계 재구성 가능한 전하 샘플러 기반 고차 시간상 이동평균 필터의 구현 및 검증 Editorial Correspondence

Jaeha Kim, Chulwoo Kim, Byeong-Gyu Nam
2016 IDEC Journal of Integrated Circuits and Systems   unpublished
The core is implemented based on a 5-stage pipeline architecture and achieves 512 MHz operating frequency with 44 k equivalent gates in a 65 nm CMOS process.  ...  Abstract -A CMOS Image Sensor (CIS) mounted on a security system does not always record a picture in a high resolution mode.  ...  Jeong-Heum Abstract -This paper proposes an efficient method to improve the performance of the projected mutual capacitance large touch screen panels (TSPs) based on differential offset cancellation technique  ... 

Automated conversion from LUT-based FPGAs to LUT-based MPGAs [article]

Francisco Javier Veredas Ramirez, Universität Ulm, Universität Ulm
In comparison with an FPGA, the area is reduced by 82 % in the logic and by up-to 64 % in the whole device.  ...  Field-programmable gate-arrays (FPGAs) are used for ASIC prototyping or small volume products.  ...  rise time for 100 100 MHz or 200 MHz clock signal is around 120 ps.  ... 
doi:10.18725/oparu-381 fatcat:vx6z27v4una77duadvv6ai6qwi

FPGA-based reconfigurable on-board computing systems for space applications [article]

Toshinori Kuwahara, Universität Stuttgart, Universität Stuttgart
The purpose of the thesis is to conceptualize an application method of ground-based reconfigurable FPGA (Field Programmable Gate Array) technologies for space systems and to apply the method to the on-board  ...  The investigation is based on thorough experimental data survey and analysis of radiation effects on existing FPGA devices.  ...  Field Programmable Gate Array An FPGA is a programmable semiconductor logic device. The user can realize desired logical functions by designing the logic in programming languages.  ... 
doi:10.18419/opus-3830 fatcat:aqfaflvcmfeijo2wqfxlfvyje4

Challenges and Solutions to Next-Generation Single-Photon Imagers

Samuel Burri
Ph.D. candidates to join his group working on CMOS SPADs.  ...  Acknowledgements This thesis started, when I was working on my master thesis in the Processor Architecture Laboratory (LAP) at EPFL, and was approached by Professor Edoardo Charbon, looking for possible  ...  From a sample of 100 histograms with around 100k events each, the DNL and INL values for each code were calculated.  ... 
doi:10.5075/epfl-thesis-7136 fatcat:7motkhc6hfabxjqqrl3mgxabuq
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