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Digitally Enhanced Information Efficient Wireline Signaling

Shovon Dey
Concurrent Binary Search was used in this work to reduce the conversion time of the SAR (Successive Approximation Register) type ADC.  ...  The 4-way time-interleaved architecture achieved 4 GS/s speed with an 8-bit resolution having 39.56 dB SNDR and 48.21 dB SFDR at the Nyquist frequency. iv  ...  The ADC prototype was implemented in TSMC 65-nm CMOS GP technology. Each SAR ADC can operate up to 1-GS/s over different corners.  ... 
doi:10.7939/r3-kh9n-dk50 fatcat:nhqyxikr75bqvcptlbfypkl3py

Parallel-sampling ADC architecture for power-efficient broadband multi-carrier systems [article]

Y Yu Lin, AHM Arthur Van Roermund, JA Hans Hegt
A parallel-sampling first stage of a 12-bit pipeline ADC and a parallel-sampling frontend stage of a 4GS/s 11-bit time-interleaving SAR ADC will be presented.  ...  ADCs with a sample rate of at least 1 GS/s and SNDR greater than 48dB measured at the Nyquist frequency published at the International Solid-State Circuits Conference (ISSCC), the VLSI Circuit Symposium  ...  Acknowledgement When I was a teenager, I enjoyed climbing mountains and exploring "hidden lands". My feeling of pursuing a PhD has a lot in common with a mountain journey.  ... 
doi:10.6100/ir782336 fatcat:mxnwyvimszgc5pvz4quvrx2fvm