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A Control-Theoretic Approach for Efficient Design of Filters in DAC and Digital Audio Amplifiers

Konstantinos Tsakalis, Nikolaos Vlassopoulos, George Lentaris, Dionysios Reisis
2010 Circuits, systems, and signal processing  
The theoretical model results in a family of digital circuits whose operation is verified by computer simulations achieving a performance of Signal-to-Noise Ratio of 147 dB at a switching rate of 90 MHz  ...  A control-theoretic approach in designing Digital to Analogue Converters and Digital Amplifiers which leads to improved performance in Audio and Multimedia applications is presented in this paper.  ...  The oversampling filter is designed as a cascade of lowpass interpolating filters [10] .  ... 
doi:10.1007/s00034-010-9231-3 fatcat:f4xwizpqbfeizhdwjssog6nznu

Integrated Smart Sensor Calibration [chapter]

Gert Van Der Horn, Johan H. Huijsing
1997 Smart Sensor Interfaces  
Linearization based on piecewise-linear interpolation 63 3.2.4 Linearization based on piecewise-polynomial or spline interpolation 67 3.2.5 Linearization based on curve fitting 70 3.2.6 Conclusion  ...  Fig. 3- 9 9 Piecewise-linear interpolation, and corresponding linearization and error curve.  ...  Furthermore, the calibration function that can be integrated with a sensor will become more advanced (faster, more accurate, or a higher-order linearization).  ... 
doi:10.1007/978-1-4615-6061-6_5 fatcat:3idid4st3rbsxba7hpciul4cdq

The Philosophy of PCM

B.M. Oliver, J.R. Pierce, C.E. Shannon
1948 Proceedings of the IRE  
INTRODUCTION You don't have to deal with ADCs or DACs for long before running across this often quoted formula for the theoretical signal-tonoise ratio (SNR) of a converter.  ...  The theoretical signal-to-noise ratio can now be calculated assuming a full-scale input sinewave: The rms signal of the input signal is therefore The rms signal-to-noise ratio for an ideal N-bit converter  ...  Also for communications applications, the AD9446 16-bit, 100 MSPS ADC is optimized for high SNR (84 dB), dissipates 2.8 W, and is also designed on a BiCMOS process.  ... 
doi:10.1109/jrproc.1948.231941 fatcat:n5mzm7dp45cojmrmzpanr5zv2y

2019 Index IEEE Journal of Solid-State Circuits Vol. 54

2019 IEEE Journal of Solid-State Circuits  
., +, JSSC Feb. 2019 417-427 A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.  ...  ., +, JSSC Feb. 2019 417-427 A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.  ... 
doi:10.1109/jssc.2019.2956675 fatcat:laiuae7dtragjijttgfatsldmu

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

P. Fiala, R. Linhart
2015 Radioengineering  
This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block.  ...  Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.  ...  We also show the table with recorded K p values. GTED S-curve is determined in a similar fashion [10] . Interpolation Control Block Interpolation is controlled by a modulo-1 counter.  ... 
doi:10.13164/re.2015.0772 fatcat:xkjgdldv35dg7psiujcwvfs2t4

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Tobias Buckel, Peter Preyler, Alexander Klinkan, Damir Hamidovic, Christoph Preissl, Thomas Mayer, Stefan Tertinek, Siegfried Brandstaetter, Christian Wicpalek, Andreas Springer, Robert Weigel
2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Compared to a digital polar TX architecture utilizing an RF digital phase-locked loop with two-point phase modulation, this results in reduced frequency modulation and digital-controlled oscillator tuning  ...  Compared to a digital-quadrature TX architecture this results in a significantly reduced average and peak RF-DAC cell utilization.  ...  of the control loop.  ... 
doi:10.1109/tcsi.2018.2840844 fatcat:ldftxnxwxfcpzc55yean6qnlkq

Linearization of the sensors characteristics: a review

Tarikul Islam, S. C. Mukhopadhyay
2019 International Journal on Smart Sensing and Intelligent Systems  
This paper presents a review of different methods applied to linearize sensor characteristics reported in the literature.  ...  techniques perform the job with better flexibility and efficiency.  ...  Some lookup table-based alternative improved methods such as piecewise linear interpolation (PWLI), piecewise linear equation (PWLE), and programmable gain amplifier (PGA) has been reported.  ... 
doi:10.21307/ijssis-2019-007 fatcat:ijrfr26svbewdhra2enuesmdnm

2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI May 2019 1728-1736 A 10-b 600-2019 4911-4921 Current mirrors A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio.  ...  ., +, TCSI Aug. 2019 3162-3173 A 10-Pan, S., +, TCSI Nov. 2019 4502-4515 A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio.  ... 
doi:10.1109/tcsi.2020.2966967 fatcat:f663jj5g45e3peggn3gwn5jys4

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI June 2020 1857-1866 An 8-bit Low-Cost String DAC With Gradient Errors Suppression to Achieve 16-bit Linearity.  ...  ., +, TCSI Sept. 2020 2873-2882 An 8-bit Low-Cost String DAC With Gradient Errors Suppression to Achieve 16-bit Linearity.  ...  Yoon, J., +, 2647-2658 A −68 dB THD, 0.6 mm 2 Active Area Biosignal Acquisition System With a 40-320 Hz Duty-Cycle Controlled Filter.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

Sampling Rate Reduction for Digital Predistortion of Broadband RF Power Amplifiers

Yue Li, Xiaoyu Wang, Anding Zhu
2019 IEEE transactions on microwave theory and techniques  
DAC, as shown in Fig. 3(a) .  ...  A different work [22] employed a decomposed piecewise technique where each piecewise segment is filtered before used as basis functions.  ... 
doi:10.1109/tmtt.2019.2944813 fatcat:l6kkhquitngfppizjfr4fxtrba

RF-PA Modeling of PAPR: A Precomputed Approach to Reinforce Spectral Efficiency

Jose Alejandro Galaviz-Aguilar, Cesar Vargas-Rosales, Esteban Tlelo-Cuautle
2020 IEEE Access  
Here, a proposed model with a basis function is derived from a multivariate spline interpolation LUT-based on a three piecewise cubic-spline.  ...  The energy efficiency maximization is jointly a nonlinear (M, K) dependence with a linear gain as: α = (P out,max )/(P in,max ) * G lin (33) For a linear gain it is assumed that the expression for the  ... 
doi:10.1109/access.2020.3012610 fatcat:qmnyiausbffylhx75wvakknqcu

2019 Index IEEE Transactions on Microwave Theory and Techniques Vol. 67

2019 IEEE transactions on microwave theory and techniques  
., +, TMTT Jan. 2019 332-346 A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS.  ...  ., +, TMTT Feb. 2019 518-532 A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS.  ...  Power demand Design of Reconfigurable dB-Linear Variable-Gain Amplifier and Switchable-Order g m -C Filter in 65-nm CMOS Technology. Liu  ... 
doi:10.1109/tmtt.2019.2953035 fatcat:hyq2vngaxrcqlggu7bzcbzdyba

FPGA implementation analysis of polyphase channelizer performing sample rate change required for both matched filtering and channel frequency spacing

Mehmood Awan, Peter Koch, Chris Dick, Fred Harris
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
Thrane & Thrane A/S, Denmark.  ...  A special thanks goes to Jan Harding Thomsen and Bo Dyssegard from Thrane & Thrane A/S for their valuable discussions and suggestions throughout the system design.  ...  Figure 3 : Cascaded structure of arbitrary re-sampler and matched filter with ML control of polyphase interpolating filter.  ... 
doi:10.1109/acssc.2010.5757590 fatcat:kcp4rrawubbs7mecgkwhqxmymu

Abstracts of Current Computer Literature

1970 IEEE transactions on computers  
This paper presents a theory to three 2-bit incremental bytes, three 4-bit explain the switching behavior of MIS Array of Parallel Shift Register Chains for state-control bytes, and a 16-bit data byte  ...  A 9-bit control reghave been investigated over a temperature Data Recovery in a Photo-Digital Storage ister controls a number of additional features range of 0 to 70'C.  ... 
doi:10.1109/tc.1970.5008907 fatcat:mkbk2sj57nezvagetslzsq5l3u

A unified message-passing algorithm for MIMO-SDMA in software-defined radio

Alexander Kocian, Mihai-Alin Badiu, Bernard Henri Fleury, Francesca Martelli, Paolo Santi
2017 EURASIP Journal on Wireless Communications and Networking  
Our receiver is implemented on a software-defined radio platform dubbed MIMONet, composed of a GNU radio software component and a universal software radio peripheral (USRP).  ...  As a use-case, we consider the high-rate packet-oriented IEEE 802.11n standard.  ...  The composite MIMO channel estimates at all active tones,Ĥ, is obtained by piecewise linear interpolation. The decorrelating MIMO multiuser detector outputs the signal x Ĥ −1 y.  ... 
doi:10.1186/s13638-016-0786-y fatcat:3z3e4w3a4bd7vb7fmi6l4zywpm
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